Vertical TFT Bit-Line Connector for Compact 3D Memory Arrays
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Solution Overview
Problem
Existing 3-D memory arrays face challenges in efficiently connecting bit lines to sense amplifiers due to the requirement for multiple conductive layers, which increases the semiconductor substrate area and limits scalability.
Innovation Solution
The implementation of vertical thin-film transistors (TFTs) above, below, or alongside the staircase structure in 3-D memory arrays, reducing the need for additional conductive layers by using metal silicide layers and specific fabrication processes to enhance current flow and reduce defect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple conductive layers are used to connect bit lines to sense amplifiers in 3-D memory arrays, then the connection functionality is achieved, but the semiconductor substrate area increases and scalability is limited
Solution Approach 1:
The patent transitions from planar 2-D conductor routing to vertical 3-D TFT structures. The vertical TFTs extend in the Z-direction perpendicular to the substrate, allowing bit line connections to sense amplifiers through the third dimension rather than requiring multiple lateral conductive layers, thus reducing substrate footprint while maintaining connection functionality
Solution Approach 2:
The vertical TFT structure nests multiple functional components (gate, channel, source, drain) within a compact vertical stack. The gate wraps around the channel in a nested configuration, and the entire TFT structure is integrated within the 3-D memory array stack, achieving high functionality in a compact footprint
2Area of stationary object
If vertical thin-film transistors are implemented to reduce substrate footprint, then the area is minimized, but the manufacturing process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct modular steps: forming the channel layer, depositing gate material, creating source/drain regions, and forming contact holes. Each step is independently controllable and can be optimized separately, making the complex vertical TFT fabrication manageable through systematic segmentation of the manufacturing process
Solution Approach 2:
The channel layer is formed and positioned before the gate and contact structures are created. This preliminary action establishes the vertical foundation that guides subsequent fabrication steps, ensuring proper alignment and reducing the complexity of later processing stages
3Reliability
If metal silicide layers are used to enhance current flow, then charge carrier mobility increases, but the manufacturing precision requirements increase
Solution Approach 1:
The metal silicide layer parameters (thickness, composition, doping concentration) are optimized to achieve the desired balance between current flow enhancement and manufacturing feasibility. By carefully controlling these parameters, the patent achieves improved charge carrier mobility while maintaining compatibility with standard fabrication capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the footprint on the semiconductor substrate, reduces the number of conductive layers required, and increases the mobility of charge carriers, thereby improving the efficiency and scalability of bit-line selection in 3-D memory arrays.
Implementation Method 1
using metal silicide layers and specific fabrication processes to enhance current flow and reduce defect density
Data Source
AI summary
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.