Vertical TFT Bit-Line Connectors for Compact 3D Memory Arrays
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Solution Overview
Problem
Existing 3-dimensional memory arrays face challenges with high defect densities and inefficient electrical connections between bit lines and support circuitry, leading to increased semiconductor substrate area requirements.
Innovation Solution
The use of low defect-density thin-film transistors (TFTs) formed above, below, or alongside the staircase structure in the 3-D memory array, utilizing metal silicide layers to facilitate electrical connections between bit lines and support circuitry, reducing the need for additional conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional horizontal transistors are used for bit-line connections in 3-D memory arrays, then electrical connections can be established, but the semiconductor substrate area increases and defect density increases
Solution Approach 1:
The patent transitions from conventional horizontal planar transistors to vertical transistors that extend in the Z-direction perpendicular to the substrate. This dimensional change allows bit-line connections to be formed vertically through the memory array layers, reducing the horizontal footprint on the semiconductor substrate while maintaining electrical connection functionality.
Solution Approach 2:
The vertical transistor structure is nested within the 3-D memory array architecture, with the transistor channel extending vertically through multiple memory string layers. The bit-line connector transistor is integrated alongside the memory strings, sharing the vertical space and reducing the need for separate horizontal connection areas.
2Ease of operation
If additional conductive layers are added to improve electrical connections, then connection efficiency improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The vertical transistor serves multiple functions: it acts as both a memory cell transistor and a bit-line connector. The same vertical transistor structure that stores data also provides the electrical connection pathway to the bit-line, eliminating the need for separate dedicated connection structures and reducing overall device complexity.
Solution Approach 2:
The patent merges the bit-line connection function with the memory storage function by using the vertical transistor to perform both roles. The drain or source region of the vertical transistor is directly connected to the bit-line, combining what would traditionally be separate functional elements into a single integrated structure.
3Power
If vertical TFTs with high mobility are used, then current capability increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes key parameters of the vertical TFT including channel width, channel length, and doping concentrations to achieve high carrier mobility. By carefully controlling these parameters during fabrication, the design achieves improved current capability while maintaining compatibility with existing manufacturing processes and precision capabilities.
Data Source
AI summary
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.