Vertical TFT Channel Structure for Short-Channel Display Integration
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Solution Overview
Problem
Conventional thin-film transistors (TFTs) face challenges in achieving short channel lengths and reducing area occupancy due to limitations in mask pattern sizes, hindering integration improvements and operational efficiency in display devices.
Innovation Solution
A semiconductor device design featuring a stacked arrangement of active layers with a through hole and a third active layer on the sidewall of the hole, allowing for a channel length determined by the through hole's depth and angle, reducing the channel length and area occupancy while enhancing on-state current and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar thin-film transistors are used with traditional mask fabrication, then manufacturing process is simple, but channel length cannot be shortened below 2 microns due to mask pattern size limitations
Solution Approach 1:
The patent transitions from a planar 2D transistor structure to a 3D vertically stacked structure. The active layer is folded back onto itself to form a U-shape or zigzag pattern, creating a vertical channel that extends in the third dimension. This allows the channel length to be determined by the vertical depth of the structure rather than being constrained by lateral mask pattern dimensions, enabling sub-2-micron channel lengths using conventional fabrication processes.
Solution Approach 2:
The active layer is folded back onto itself, creating a nested configuration where portions of the active layer are stacked vertically. This nesting allows the channel to be formed within a compact lateral footprint while achieving extended vertical channel length, effectively packing more channel length into a smaller planar area.
2Area of stationary object
If thin-film transistors are made smaller to reduce area occupancy, then integration density improves, but electrical performance deteriorates due to excessive shortening of channel length
Solution Approach 1:
By transitioning to a vertical stacked architecture, the patent decouples the relationship between lateral transistor dimensions and channel length. The channel length is now defined by the vertical extent of the folded active layer rather than the lateral distance between source and drain contacts. This allows the transistor footprint to be minimized for high integration density while maintaining adequate channel length for proper electrical performance through vertical stacking.
Solution Approach 2:
The patent applies different functional regions within the active layer: the folded portions forming the vertical channel have optimized thickness and doping for charge transport, while the contact regions are optimized for electrical connection. This local optimization allows each region to perform its specific function effectively, maintaining electrical performance despite reduced overall transistor area.
3Productivity
If channel length is shortened to improve switching speed and reduce power consumption, then operational efficiency improves, but short-channel effects increase making device control difficult
Solution Approach 1:
The patent implements selective doping in different regions of the active layer. The channel region has optimized doping concentration to balance carrier mobility and threshold voltage control, while the contact regions have higher doping for low resistance connections. This local quality differentiation allows the short channel to operate efficiently while maintaining controllability through region-specific property optimization.
Solution Approach 2:
The patent optimizes the thickness of the active layer in the vertical channel region to achieve the desired balance between switching speed and short-channel effect suppression. By carefully controlling the active layer thickness parameter in the folded region, the device achieves fast switching while maintaining adequate gate control over the channel, preventing excessive short-channel effects despite the short lateral dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves shorter channel lengths, reduces power consumption, and improves integration, facilitating high pixel density and refresh rates in display devices, with potential for integrated circuit functions.
Implementation Method 1
at least part of the third active layer is located on a sidewall of the through hole, one side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer
Implementation Method 2
the first active layer includes a first conductor portion doped with ions, and the second active layer includes a second conductor portion doped with ions
Data Source
AI summary
A semiconductor device and an electronic device are provided. A through hole is formed in an insulating layer and located on a first active layer. A thin-film transistor layer includes a third active layer. At least part of the third active layer is located on a sidewall of the through hole. One side of the third active layer is connected to a first active layer, and the other side of the third active layer is connected to a second active layer, so that a channel length is reduced, short channel effect is reduced, on-state current is increased, and power consumption is reduced.