Vertical Thin-Film Transistor Structure for Low-Current Cognitive Circuits
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Solution Overview
Problem
Existing transistor devices with higher current are not suitable for cognitive device circuits that require lower current specifications for proper operation, leading to signal delay issues.
Innovation Solution
Development of a vertically disposed thin film transistor (TFT) with low mobility and low current properties, fabricated at the substrate surface as a front end of the line (FEOL) or back end of the line (BEOL), utilizing materials and doping levels in the source, drain, and channel layers to achieve high resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If higher current transistor devices are used, then signal delay is reduced, but they are not suitable for cognitive device circuits that require lower current specifications
Solution Approach 1:
The patent changes the electrical parameters of the transistor by adjusting doping levels in the source, drain, and channel layers, and by selecting specific material compositions. This allows tuning the transistor to operate at low current levels while maintaining appropriate resistance characteristics for cognitive device circuits, resolving the contradiction between current consumption and signal delay
Solution Approach 2:
The patent employs composite material structures with multiple layers having different compositions and doping levels. The source, drain, and channel layers are formed with specific material combinations that enable low current operation with high resistance, suitable for cognitive devices while managing signal delay through optimized material properties
2Use of energy by moving object
If vertically disposed TFT with low mobility and high resistance is used, then current is reduced for cognitive devices, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into multiple distinct layers (source layer, channel layer, drain layer) with different materials and doping levels. This segmentation allows independent optimization of each layer's properties to achieve low mobility and high resistance while using standard thin-film fabrication techniques, managing manufacturing complexity through modular layer design
Solution Approach 2:
The patent applies different material compositions and doping levels to specific regions (source, channel, drain) of the transistor. Each region has locally optimized properties: the channel layer has low mobility characteristics for high resistance, while source and drain layers have appropriate doping for contact formation. This local quality approach achieves the desired electrical characteristics without requiring complex manufacturing processes
Data Source
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AI summary
A vertical transistor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.