Vertical TFT Structure for Short-Channel Control and Ion Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional thin-film transistors (TFTs) face challenges in achieving a short channel length due to limitations in manufacturing processes, leading to increased short-channel effects, reduced on-state current, and higher power consumption, which hinder the development of high-resolution and low-power display devices.
Innovation Solution
A vertical structure TFT design is implemented, featuring an active layer with a first conductive part, an active section, and a second conductive part stacked on an insulating substrate, where the second conductive part is thicker than the first, and both are doped with ions, reducing channel length and preventing contamination ion diffusion, thereby enhancing reliability and reducing short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length of conventional TFTs is reduced to increase integration degree and reduce size, then the TFT size and channel length decrease, but short-channel effects increase and gate control capability deteriorates
Solution Approach 1:
The patent transitions from a conventional planar TFT structure to a vertical TFT structure where the active layer extends in the thickness direction (vertical dimension) rather than only in the plane. The active layer includes a first conductive part, an active section, and a second conductive part stacked vertically, with the gate electrode wrapping around the active layer laterally. This dimensional change allows the channel to be short in the plane (reducing TFT size) while maintaining effective gate control through the lateral wrap-around configuration.
2Productivity
If the channel length is reduced to increase integration density, then more devices can be integrated, but subthreshold leakage phenomenon increases
Solution Approach 1:
By stacking the active layer vertically with the gate electrode wrapping around it laterally, the invention achieves short channel length in the plane (increasing integration density) while maintaining effective gate control that suppresses subthreshold leakage through the three-dimensional field effect.
Solution Approach 2:
The patent optimizes the thickness of the active layer (controlling the vertical dimension of the channel) and the doping concentration of the conductive parts to balance short-channel effect suppression with leakage reduction, enabling high integration density while maintaining device reliability.
3Ease of manufacture
If conventional manufacturing processes are used to pattern the active layer, then the manufacturing process remains simple, but the minimum pattern size is greater than 2 μm preventing short channel realization
Solution Approach 1:
The vertical stacking configuration allows the channel length to be defined by the thickness of the active layer rather than by planar photolithography patterning. This enables sub-2 μm effective channel lengths to be achieved through thin-film deposition thickness control, which has higher precision than conventional optical lithography, while still using standard manufacturing processes.
4Area of moving object
If the distance between source and drain is reduced to decrease TFT size, then the device area decreases, but the gate control capability over the channel deteriorates
Solution Approach 1:
The gate electrode is configured to wrap around the active layer laterally, extending over the top surface and down the side surfaces. This three-dimensional gate configuration maintains strong electrostatic control over the channel even when the planar distance between source and drain is reduced, as the gate field acts from multiple directions (top and lateral sides) rather than only from above.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure TFTs achieve improved reliability, increased on-state current, reduced power consumption, and higher integration density, enabling the development of high pixels per inch and high refresh rate display devices with enhanced IC functions.
Implementation Method 1
the active layer comprises a first active layer, a second active layer, and a third active layer which are stacked and disposed on the insulating substrate; wherein the active layer comprises the first conductive part doped with an ion, and the third active layer comprises the second conductive part doped with an ion
Implementation Method 2
an active layer disposed on the insulating substrate, wherein the active layer comprises a first conductive part, an active section, and a second conductive part which are stacked; wherein an orthographic projection of the first conductive part on the insulating substrate partly overlaps an orthographic projection of the second conductive part on the insulating substrate
Implementation Method 3
an orthographic projection of the first conductive part on the insulating substrate partly overlaps an orthographic projection of the second conductive part on the insulating substrate
Data Source
AI summary
A thin-film transistor (TFT) having a vertical structure and an electronic device are provided. The TFT having the vertical structure includes an insulating substrate and an active layer disposed on the insulating substrate. The active layer includes a first conductive part, an active section, and a second conductive part which are stacked. An orthographic projection of the first conductive part on the insulating substrate partly overlaps an orthographic projection of the second conductive part on the insulating substrate. Therefore, contamination ions may be prevented from entering the active section from the insulating substrate during manufacturing processes of the TFT. Thus, reliability of performance of the TFT may be improved.