Vertical Thin Film Transistor with ITZO Semiconductor
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Solution Overview
Problem
Current thin film transistors (TFTs) face challenges in achieving improved electrical characteristics and process margins, particularly in highly-integrated high-performance electronic devices, where minimizing occupied area and enhancing electron mobility are crucial.
Innovation Solution
A vertical-type TFT structure is developed, featuring a stacked configuration with different metal materials for the second and third electrodes, utilizing an indium-tin-zinc-oxide (ITZO) semiconductor pattern, and a method that includes forming specific contact holes and connection patterns to optimize the channel region through controlled thickness and offset regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional planar TFT structure is used, then the manufacturing process is simple, but the occupied area is large and electron mobility is limited
Solution Approach 1:
The patent transitions from a planar TFT structure to a vertical stacked structure, moving the current path from a two-dimensional plane to a three-dimensional vertical configuration. This dimensional change enables shorter channel lengths and improved electron mobility while maintaining a compact footprint, directly resolving the contradiction between productivity (electron mobility) and device complexity
2Area of stationary object
If the TFT occupied area is minimized for high integration, then device density increases, but electrical characteristics and process margin deteriorate
Solution Approach 1:
By stacking electrodes and semiconductor layers vertically, the patent achieves miniaturization in the planar area while preserving electrical characteristics through the vertical current path. The offset region design further ensures reliable electrical performance despite the compact footprint, resolving the contradiction between area minimization and reliability
Solution Approach 2:
The vertical stacked structure nests multiple functional layers (first electrode, second electrode, third electrode, semiconductor pattern) within a compact vertical space. This nesting approach allows the TFT to maintain full electrical functionality while occupying minimal planar area, addressing both area reduction and characteristic preservation
3Productivity
If oxide semiconductor material is used instead of silicon-based material, then electron mobility and on/off current ratio improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs low-temperature manufacturing processes and controls deposition parameters to achieve uniform oxide semiconductor patterns. By optimizing process parameters such as deposition temperature, pressure, and material composition, the patent maintains high manufacturing precision while utilizing oxide semiconductor materials for improved electron mobility
Data Source
AI summary
Provided is a thin film transistor (TFT) that includes a first electrode on a substrate separated from a second electrode, an oxide semiconductor pattern on the second electrode including a channel region, a third electrode on the oxide semiconductor pattern, a first insulating layer on the substrate including the third electrode including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode, a gate electrode on the first insulating layer and corresponding to a part of the oxide semiconductor pattern, a second insulating layer on the substrate including the gate electrode including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode, and a pixel electrode on the second insulating layer electrically connected to the second electrode through the first contact hole and the second contact hole.