Vertical TFT Architecture for Low-Leakage Memory Selectors
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Solution Overview
Problem
Silicon transistors used as selectors in memory devices are leaky, affecting the performance of storage cells, and thin-film transistors (TFTs) are difficult to scale with advancing fabrication technologies.
Innovation Solution
A TFT with a vertical architecture in multiple metal layers is developed, where the source and drain electrodes are in parallel in one direction, and the gate electrode is orthogonal to them, allowing for better electrostatic control and easier integration, with individually designed contacts for improved RC circuit benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon transistor is used as a selector in a memory cell, then the transistor can control access to the storage cell, but the transistor becomes leaky which adversely impacts storage cell performance
Solution Approach 1:
The patent changes the material parameter from silicon to thin-film transistor materials, and changes the structural parameter from planar to vertical architecture. This transforms the transistor's electrical characteristics to reduce leakage while maintaining control functionality in memory cell selectors
2Loss of energy
If a thin-film transistor (TFT) is used as a selector in a memory cell, then the transistor can reduce leakage compared to silicon transistors, but the TFT becomes difficult to scale with advancing fabrication technologies
Solution Approach 1:
The patent transitions from two-dimensional planar TFT architecture to three-dimensional vertical architecture. This dimensional change enables better scaling by utilizing the vertical dimension for channel length control while maintaining larger lateral dimensions for easier fabrication and integration with existing processes
3Ease of operation
If a vertical architecture with multiple metal layers is used for TFT, then the electrostatic control and integration are improved, but the device structure becomes more complex
Solution Approach 1:
The patent segments the gate electrode into multiple metal layers (first gate electrode in one metal layer, second gate electrode in another metal layer). This segmentation provides independent control of different channel regions, improving electrostatic control and enabling separate optimization of threshold voltage and channel conduction
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.