Vertical TFT MRAM Access Transistors for High Drive Current Density
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in providing sufficient drive current for memory technologies like MRAM, and in achieving high integration density due to space constraints in the Front End of Line (FEOL) of fabrication processes.
Innovation Solution
The integration scheme uses a plurality of vertical thin-film transistors (TFTs) connected in parallel as access transistors to provide a drive current for memory technologies. These TFTs are formed at low temperatures in the Back End of Line (BEOL) and are used to form MRAM cells, allowing for customization of device parameters and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional access transistors are used in FEOL, then manufacturing process is simplified, but drive current is insufficient for MRAM cells
Solution Approach 1:
The fabrication process is segmented into two distinct stages: FEOL for logic circuit formation and BEOL for memory array formation. This allows conventional FEOL transistors to be used for logic while specialized high-current transistors are formed in BEOL specifically for driving MRAM cells, resolving the contradiction between manufacturing simplicity and drive current requirements.
Solution Approach 2:
The access transistors are relocated from the traditional FEOL plane to the BEOL vertical dimension. By forming transistors in the back-end interconnect layers rather than in the front-end substrate, the patent achieves higher drive currents while maintaining FEOL manufacturing simplicity for logic circuits.
2Power
If more space is allocated for access transistors, then drive current increases, but integration density decreases
Solution Approach 1:
By moving access transistor formation to the vertical BEOL dimension rather than expanding horizontal FEOL area, the patent achieves both higher drive currents and higher integration density. The BEOL space utilization enables larger transistor dimensions for current drive without reducing the dense FEOL memory array layout.
3Productivity
If FEOL space is used for memory arrays, then integration density is maximized, but no space remains for high-current access transistors
Solution Approach 1:
The patent segments the device into FEOL logic/memory formation and BEOL access transistor formation. This allows the FEOL to be fully utilized for high-density memory arrays while the BEOL provides dedicated space for large-area high-current transistors, eliminating the space trade-off.
Solution Approach 2:
Access transistors are formed in the vertical BEOL dimension rather than competing for horizontal FEOL space. This dimensional separation enables maximum integration density in FEOL while providing sufficient area in BEOL for high-current drive capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher available drive currents for MRAM cells and allows for higher integration density by utilizing space in the FEOL for other purposes, while also enabling the formation of multi-stack memory arrays through monolithic integration.
Implementation Method 1
One type of non-volatile semiconductor memory is magnetoresistive random access memory (MRAM), which involves spin electronics that combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, are used to indicate bit values.
Implementation Method 2
The spins of electrons, through their magnetic moments, are used to indicate bit values.
Implementation Method 3
A MRAM cell typically includes a magnetic tunnel junction (MTJ) stack, which includes a pinned magnetic layer, a free magnetic layer, and a tunneling non-magnetic barrier layer between the pinned layer and the free layer.
Data Source
AI summary
In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.