Vertical Thin-Film Transistor Layout for Ultra-High Pixel Density
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Solution Overview
Problem
The existing thin film transistor structures occupy a large area in a plane, making it difficult to meet the requirements for ultra-high pixel density in display panels, as they cannot efficiently accommodate the increasing number of pixels and transistors needed for virtual and augmented reality applications.
Innovation Solution
A thin film transistor design where the drain, source, and active layer are arranged in different layers, overlapping each other vertically, reducing the occupied area and allowing for a more compact arrangement of transistors in a unit area, which includes a gate that overlaps with the drain, source, and active layer, and a via structure that connects the source and drain with a recessed active layer, reducing the overall plane area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the drain, source, and active layer are arranged in the same layer horizontally, then the transistor structure is simple and easy to manufacture, but the area occupied by the transistor in a plane is large
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement to a three-dimensional stacked arrangement by placing the drain, source, and active layer in different layers vertically. Specifically, the active layer is formed on the base substrate, the drain is formed on one side of the active layer, and the source is formed on the other side of the active layer, creating a vertical channel structure that significantly reduces the planar area occupied by each transistor.
Solution Approach 2:
The patent implements a nested structure where the drain and source are positioned on opposite sides of the active layer in a stacked configuration. The gate wraps around the active layer, with portions positioned above and below the active layer, creating a nested arrangement where control elements surround the channel-forming elements, maximizing spatial efficiency.
2Quantity of substance
If more thin film transistors are arranged in a unit area to achieve ultra-high PPI, then the pixel density increases, but the area occupied by each transistor must be reduced which complicates the transistor design
Solution Approach 1:
By arranging the drain, source, and active layer in a vertical stacked configuration across multiple layers, the patent reduces the planar footprint of each transistor. This vertical integration allows a higher density of transistors to be packed into a given area while maintaining manufacturability through standard thin-film deposition and patterning processes.
Solution Approach 2:
The transistor is segmented into distinct functional layers: the active layer forms the channel on the base substrate, the drain and source are segmented and positioned on opposite sides of the active layer in upper layers, and the gate is segmented into portions that wrap around the active layer. This segmentation allows each component to be optimized independently while achieving high density.
3Area of stationary object
If the gate overlaps with the drain, source, and active layer vertically, then the transistor area is minimized, but the manufacturing process becomes more complex with multiple layers and vias
Solution Approach 1:
The gate is positioned in multiple layers with portions above and below the active layer, creating a wrapped configuration that maximizes overlap and minimizes area. The multi-layer structure includes intermediate insulating layers and conductive layers that can be formed using standard thin-film deposition techniques, maintaining manufacturing feasibility despite the increased vertical complexity.
Data Source
AI summary
A thin film transistor including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other.