Vertical TFT Select Devices for 3D Memory Density
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Solution Overview
Problem
Existing three-dimensional non-volatile memory arrays face challenges in achieving high density and efficient operation due to the need for complex stacking of memory levels and the requirement for precise control of select device performance in vertically-oriented memory elements.
Innovation Solution
The implementation of a vertically-oriented thin film transistor (TFT) select device in a three-dimensional memory array, which includes a select device pillar with a body and source/drain regions, a gate dielectric, and a conformal deposition process for the base dielectric layer and hard mask formation to control gate bottom height and select device performance, allowing for tight control of select device operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-oriented TFT select devices are implemented in 3D memory arrays, then memory density and select device performance are improved, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent transitions from planar TFT select devices to vertically-oriented TFT select devices, changing the dimensional orientation from 2D to 3D. This vertical orientation allows multiple memory levels to be stacked while maintaining efficient select device performance, thereby increasing memory density without proportionally increasing manufacturing complexity
Solution Approach 2:
The vertically-oriented TFT select device is segmented into distinct functional regions including a body portion, upper source/drain regions, and lower source/drain regions. This segmentation allows for optimized fabrication processes where each region can be formed with specific characteristics, managing the overall manufacturing complexity through modular construction
2Manufacturing precision
If conformal deposition processes are used for base dielectric and hard mask formation, then gate bottom height control precision is improved, but process time and manufacturing complexity increase
Solution Approach 1:
The base dielectric layer and hard mask layer are formed using conformal deposition processes before the gate electrode is created. This preliminary action establishes precise thickness profiles and uniform coverage in advance, ensuring accurate gate bottom height control when subsequent etching and gate formation steps are performed
Solution Approach 2:
A hard mask layer is deposited as an intermediary between the base dielectric layer and the gate electrode formation process. This intermediary layer provides a controlled etch stop and defines the gate bottom height precisely, allowing for accurate dimensional control while managing the overall process complexity
3Ease of operation
If vertically-oriented TFTs are used to connect local and global bit lines, then voltage control efficiency is improved, but device structure complexity increases
Solution Approach 1:
The select device is oriented vertically to connect local bit lines at different vertical levels to global bit lines. This vertical configuration provides direct electrical pathways through the memory stack, improving voltage control efficiency by reducing the number of intermediate connections and parasitic resistances compared to lateral routing
Solution Approach 2:
The vertically-oriented TFT select device serves multiple functions: it acts as a switch to control current flow between local and global bit lines, provides electrical isolation between different memory levels, and enables voltage control for SET, RESET, and FORM operations. This multi-functionality improves operational efficiency while the modular vertical structure manages the inherent complexity
Data Source
AI summary
Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.