Vertical Oxide TFT Self-Aligned Doping for Low Contact Resistance
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Solution Overview
Problem
Oxide thin-film transistors with vertical channels require an impurity region to reduce contact resistance, but existing manufacturing methods are inefficient and lack a self-doped state without separate impurity regions.
Innovation Solution
A thin film transistor manufacturing method involving the formation of a gate insulation film and a doped layer using self-alignment techniques to create impurity regions on both sides of the active layer, eliminating the need for separate impurity regions and improving productivity by removing photolithography and ion implantation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate impurity regions are formed using conventional methods (photolithography and ion implantation), then contact resistance between source/drain electrodes and active layer is reduced, but manufacturing complexity and process time increase
Solution Approach 1:
The gate insulation film serves a dual function: as the gate dielectric layer and as a mask for self-aligning the impurity regions. The spacer layers automatically define the precise location where impurity regions form through selective etching, eliminating the need for separate photolithography alignment steps. The structure self-organizes to create properly positioned impurity regions without external intervention.
Solution Approach 2:
The gate insulation film formation and impurity region definition processes are merged into a single self-aligned operation. The spacer layers and etching process simultaneously define both the gate electrode boundaries and the impurity region locations, combining multiple functions into one integrated process step.
2Reliability
If separate impurity regions are formed using photolithography and ion implantation, then contact resistance is reduced, but manufacturing time and productivity decrease
Solution Approach 1:
The structure automatically defines impurity region locations through the spacer layer geometry and selective etching, eliminating time-consuming photolithography alignment and separate ion implantation steps. The self-aligned process reduces the number of discrete manufacturing steps while maintaining precise impurity region positioning.
Solution Approach 2:
The spacer layers are formed in advance with precise dimensions that pre-determine the future impurity region locations. This preliminary structuring allows subsequent etching to automatically create correctly positioned impurity regions without requiring real-time alignment or positioning operations.
3Ease of manufacture
If oxide thin-film transistors use self-doped state without separate impurity regions, then manufacturing simplicity increases, but contact resistance between source/drain electrodes and active layer increases
Solution Approach 1:
Impurity regions are created only in specific localized areas where source/drain electrodes contact the active layer, while the rest of the active layer maintains its intrinsic oxide semiconductor properties. The selective etching of spacer layers ensures impurities are introduced only where needed for contact resistance reduction, preserving the advantages of self-doped oxide semiconductors in the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances productivity by forming impurity regions through self-alignment techniques, reducing contact resistance and improving the manufacturing efficiency of oxide semiconductor thin-film transistors with vertical channels.
Implementation Method 1
forming a doped layer on the gate insulation film and the active layer outside the gate insulation film to form impurity regions
Data Source
AI summary
An embodiment of the inventive concept provides a thin film transistor and a manufacturing method of the same. The manufacturing method includes forming a data electrode on one side of a substrate, forming a spacer layer on a portion of the data electrode and the other side of the substrate, forming a drain electrode on a top surface of the spacer layer, forming an active layer on a sidewall of the spacer layer, the drain electrode, and the data electrode, forming a gate insulation film that covers the active layer on the sidewall of the spacer layer, and forming a doped layer on the gate insulation film and the active layer outside the gate insulation film to form impurity regions at both sides, respectively, of the active layer.