Vertical Thin Film Transistors with Shared Bitlines
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Solution Overview
Problem
Conventional thin-film transistors face limitations in scaling down due to variability in fabrication processes, particularly in the sub-10 nm range, which hampers the integration of advanced semiconductor devices and increases thermal sensitivity, affecting performance and channel mobility.
Innovation Solution
The implementation of non-planar BEOL-compatible thin film transistors with increased transistor width and shared bitlines, utilizing semiconducting oxide materials like IGZO, and advanced architectures such as vertical width TFTs with conductive contacts extending through multiple interconnect levels, enhances gate control and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional thin-film transistors are scaled down to sub-10 nm range, then integration density increases, but fabrication process variability worsens and thermal sensitivity increases
Solution Approach 1:
The patent transitions from planar 2D transistor channels to three-dimensional vertical channels extending through multiple interconnect levels (BL0, BL1, BL2). This dimensional change increases the effective channel width without proportionally increasing the footprint area, achieving higher integration density while maintaining manufacturable feature sizes that are less susceptible to fabrication variability
Solution Approach 2:
The patent embeds multiple bitlines (BL0, BL1, BL2) and conductive contacts within the vertical channel structure, with conductive contacts extending through interconnect levels to connect drains of multiple transistors. This nesting approach increases functional density while using shared bitlines to reduce the number of separate interconnect structures needed
2Power
If transistor width is increased to improve drive strength, then performance increases, but area occupied by each transistor increases
Solution Approach 1:
The patent creates vertical channels that extend through multiple interconnect levels (at least two levels), effectively increasing the channel width in the vertical dimension while maintaining a compact horizontal footprint. This allows higher drive strength without proportionally increasing the area occupied by each transistor
Solution Approach 2:
Adjacent transistors share common bitlines (e.g., drains of multiple transistors connected to the same bitline through conductive contacts), merging interconnect resources. This sharing reduces the total area required for interconnect structures and allows higher effective transistor width while controlling overall device area
Data Source
AI summary
Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.