Vertical TFT Short-Channel Effect Suppression
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Solution Overview
Problem
Current vertical thin film transistors (VTFTs) face limitations in high-speed switching due to short-channel effects and large size, which restrict their application in high-resolution display devices and imaging electronics.
Innovation Solution
Incorporating counter-doped intermediate semiconductor layers between the ohmic contact layers and the dielectric in the VTFT structure to suppress short-channel effects and reduce channel length, allowing for smaller TFT size and improved switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is reduced to improve switching speed, then high-speed switching is achieved, but short-channel effects increase
Solution Approach 1:
An intermediate layer with opposite doping type is introduced between the ohmic contact layer and the dielectric layer. This intermediate layer acts as a mediator that suppresses short-channel effects by creating a depletion region that prevents carrier accumulation at the dielectric interface, thereby maintaining device reliability even with reduced channel length
Solution Approach 2:
The doping concentration and type are varied locally within the semiconductor structure. The ohmic contact layer has one doping type while the intermediate layer has the opposite doping type, creating localized regions with different electrical properties. This local quality variation enables simultaneous achievement of low contact resistance and short-channel effect suppression
2Area of moving object
If the TFT size is reduced to improve pixel fill factor, then higher resolution is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The transistor structure transitions from a planar layout to a vertical stacked configuration. The channel, gate, source, and drain are arranged in vertical layers rather than horizontal planes, allowing the TFT to occupy minimal lateral area while maintaining functional integrity. This dimensional change enables small TFT footprint without proportionally increasing fabrication complexity
Solution Approach 2:
The semiconductor structure is segmented into distinct functional layers: ohmic contact layer, intermediate layer, dielectric layer, and channel layer. Each layer performs a specific function and can be independently optimized and fabricated, reducing the overall manufacturing precision requirements compared to a monolithic structure
3Length of moving object
If the channel length is scaled down to nanoscale to reduce TFT size, then pixel area is minimized, but short-channel effects become severe
Solution Approach 1:
The intermediate layer with opposite doping type is positioned beforehand between the ohmic contact and dielectric layers to preemptively counteract short-channel effects. By creating a depletion region in advance, it prevents harmful carrier accumulation and electric field distortion before they can develop in the nanoscale channel
Solution Approach 2:
The doping parameters (type and concentration) are changed in the intermediate layer compared to the ohmic contact layer. This parameter change creates a doping profile that generates a depletion region, fundamentally altering the electrical characteristics to suppress short-channel effects in the nanoscale channel
Data Source
AI summary
A vertical thin film transistor (TFT) structure allows for a channel length to be scaled down, below that allowed by lateral TFT structures, to nanoscale (i.e., below 100 nm). However, while reducing the channel length, short-channel effects have been found in previous VTFT structures. Aspects of the new vertical TFT structure allow for the suppression of some of the short-channel effects. Advantageously, the capability of defining nanoscale channel length with short-channel effect suppression allows for p-channel vertical TFTs, where previously these were impractical. Furthermore, in aspects of the vertical TFT structure, the gate electrode is entirely vertical and by eliminating the horizontal overlap of the gate electrode over the drain electrode that present in earlier vertical TFT structures, parasitic gate-to-drain capacitance is eliminated. The vertical TFT structure provides size advantages over lateral TFTs and, furthermore, allows a TFT to be built at the intersection of electrode lines in an active-matrix configuration.