Vertical TFT Top-Gate Structure for Simplified Manufacturing
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Solution Overview
Problem
Current semiconductor device manufacturing processes for vertical TFTs are complex and costly, with limitations in achieving small feature sizes and high drive current at low voltage, and there is a need for simpler methods to pattern devices with critical vertical features and control transistor behavior in circuit design.
Innovation Solution
The development of a semiconductor device architecture featuring a substrate with a vertical-support-element having a reentrant profile, where a conformal semiconductor layer and electrodes define a transistor channel, allowing for the use of selective area deposition and atomic layer deposition to create high-quality thin films without the need for high-resolution alignments, enabling the fabrication of multiple transistor types on a common substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithographic patterning methods are used, then feature size can be controlled, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent extracts the patterning function from the complex photolithographic process by using selective area deposition on vertical walls. The vertical wall structure itself serves as the pattern definition, eliminating the need for multiple photolithographic steps, alignements, and etching processes while maintaining precise feature size control.
Solution Approach 2:
The patent introduces a vertical wall structure as an intermediary element that simplifies the patterning process. This vertical wall acts as a self-aligning mask and pattern definition, allowing direct deposition of functional layers without requiring complex photolithographic alignment and etching sequences.
2Length of moving object
If photolithographic techniques with complex semiconductor processes are used, then short channel length devices can be fabricated, but manufacturing cost increases
Solution Approach 1:
The patent transitions from planar patterning to vertical wall patterning, utilizing the vertical dimension to define the channel length. By depositing functional layers conformally on vertical walls, the channel length is precisely controlled by the vertical wall height, enabling short channel devices without requiring expensive high-resolution photolithography.
Solution Approach 2:
The patent changes the controlling parameter for channel length from lateral photolithographic dimensions to vertical deposition thickness. This parameter change allows precise channel length control through deposition process parameters rather than expensive photolithographic tools, significantly reducing manufacturing cost.
3Reliability
If complex alignment and etching processes are used, then vertical TFTs can be fabricated, but production time increases and productivity decreases
Solution Approach 1:
The patent performs preliminary action by forming the vertical wall structure before depositing functional layers. This pre-formed vertical wall serves as a self-aligning template that eliminates the need for subsequent alignment and etching steps, significantly reducing production time while maintaining device performance through conformal deposition on the pre-defined vertical structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing of vertical TFTs, reduces production costs, and enhances circuit performance by allowing for flexible transistor design and improved current handling capabilities, while eliminating the need for complex alignment and etching processes.
Implementation Method 1
allowing for the use of selective area deposition and atomic layer deposition to create high-quality thin films
Implementation Method 2
a vertical-support-element on the substrate, the vertical-support-element extending away from the substrate, the vertical-support-element including a first edge having a first reentrant profile
Data Source
AI summary
An electronic device includes a vertical-support-element on a substrate. The vertical-support-element extends away from the substrate and includes a first edge having a first reentrant profile. A conformal semiconductor layer is in contact with the vertical-support-element in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer and is located over a top of the vertical-support-element. A second electrode is in contact with a second portion of the semiconductor layer and is located over the substrate and not over the vertical-support-element. The second electrode is adjacent to the first edge of the vertical-support-element. A conformal dielectric layer is on the conformal semiconductor layer in the reentrant profile. A conformal conductive gate is on the conformal dielectric layer in the first reentrant profile. The first electrode and the second electrode define a semiconductor channel of a transistor.