Vertical Through-Die Interconnects for High-Frequency IC Stacks
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Solution Overview
Problem
Existing wire bonding techniques for semiconductor devices are limited in their ability to support high-frequency applications due to their inductive nature and the resulting length constraints of the wire bonds.
Innovation Solution
The development of a passive IC assembly with an overlapping arrangement of multi-layer IC devices that include through-device micro vias, allowing for a conductive path that traverses the entire height of the assembly, thereby reducing wire length and enhancing high-frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for electrical connection, then ease of manufacture is improved, but high-frequency performance deteriorates due to inductive nature and length constraints
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical interconnects (through-silicon vias) that penetrate the substrate thickness dimension. This dimensional change enables direct vertical connections through the substrate, eliminating the need for long lateral wire bonds and thereby reducing inductance while improving high-frequency performance
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a fabrication-based via formation process. Instead of manually or mechanically attaching wires to substrate pads, the invention uses semiconductor fabrication techniques (drilling, plating, filling) to create integrated vertical conductive paths, thereby eliminating the mechanical connection interface and its associated inductance
2Reliability
If wire bond length is reduced to improve high-frequency performance, then manufacturing complexity increases due to stricter alignment and positioning requirements
Solution Approach 1:
The patent merges the electrical connection function with the substrate structure itself by creating through-silicon vias that are an integral part of the substrate. This integration eliminates the separate wire bond component and its associated alignment requirements, as the vias are directly formed in predetermined locations within the substrate
Solution Approach 2:
The patent performs via formation, plating, and filling operations during the substrate fabrication process before final assembly. This preliminary action establishes the vertical interconnect paths in advance, eliminating the need for complex post-assembly alignment and bonding operations that would be required for shortened wire bonds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher-frequency operation by reducing the length of traditional wire bonds and providing a more efficient electrical path, which is particularly beneficial for 3D IC applications.
Implementation Method 1
a first through-device via configured to provide a first conductive path extending between the upper and lower surfaces of the first IC die
Data Source
AI summary
Aspects of the subject disclosure may include, for example, an Integrated Circuit (IC) assembly. The assembly includes a first die including a first stack of insulating layers having a first overall thickness. The first die further includes a first through-device via configured to provide a first conductive path therethrough. The IC assembly further includes a second die affixed to the first die in a stacked arrangement, the second die including a second stack of insulating layers having a second overall thickness. The second die further includes a second through-device via configured to provide a second conductive path extending therethrough. The second through-device via is electrically coupled to the first through-device via to obtain a through-assembly via configured to provide a through-assembly conductive path extending from the upper surface of the first die to the lower surface of the second die. Other embodiments are disclosed.