Vertical Thyristor 1T DRAM Layout for High-Density Memory Cells
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Solution Overview
Problem
As memory devices integrate to smaller areas, securing sufficient capacitance becomes challenging, leading to difficulties in minimizing cell dimensions and increasing integration density, particularly in Dynamic Random Access Memory (DRAM) units.
Innovation Solution
The development of a capacitor-less 1T DRAM using a vertical thyristor of PNPN structure, where a vertical thyristor is formed to minimize cell dimension, and a hybrid bonding process is used to integrate the memory cell array and peripheral circuit unit, eliminating the need for capacitors and allowing for three-terminal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of a unit cell decreases to increase integration density, then the integration degree increases, but it becomes difficult to secure sufficient capacitance
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical three-dimensional capacitor structures. The capacitor is formed extending in the vertical direction (thickness direction) rather than only in the planar direction, effectively utilizing the third dimension to increase capacitance while maintaining small unit cell area. This dimensional change allows sufficient capacitance to be achieved in highly integrated memory devices.
2Reliability
If conventional DRAM capacitors are used, then data storage function is achieved, but the structure becomes complex and requires refresh operations
Solution Approach 1:
The patent merges the capacitor structure with the transistor structure by forming the capacitor using the same vertical semiconductor pillars and doped regions that constitute the transistor. The source/drain regions of the transistor serve dual purposes as both transistor components and capacitor electrodes, eliminating the need for separate capacitor structures and reducing overall device complexity while maintaining data storage functionality.
Data Source
AI summary
A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.