Vertical Thyristor ESD Protection with Buried Bypass
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current ESD protection devices, particularly those based on lateral and vertical thyristors, face limitations such as high dynamic resistance, long switching times, and increased wafer or die area consumption, which affect their robustness and efficiency in protecting against electrostatic discharges.
Innovation Solution
A vertically integrated semiconductor device with a buried pn-short and a vertical thyristor concept, where a metal trench acts as an electrical bypass to reduce resistance and enhance holding current, preventing latch-up and allowing for low overvoltage protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically integrated devices are manufactured by forming one or more layers above each other using conventional methods, then device integration is achieved, but high dynamic resistance and long switching times occur
Solution Approach 1:
The patent transitions from lateral integration to vertical integration by stacking semiconducting layers (n-type layer 305, p-type layer 310, n-type layer 315) vertically above each other. This dimensional change enables current flow through the vertical stack, reducing switching time and dynamic resistance while maintaining ESD protection robustness.
Solution Approach 2:
The device is segmented into multiple distinct semiconducting layers with different conductivity types (n-type and p-type) stacked vertically. Each layer serves a specific function in the ESD protection mechanism, allowing optimized current paths and reducing overall switching time compared to conventional lateral structures.
2Reliability
If conventional ESD protection devices are used, then protection against electrostatic discharge is provided, but high dynamic resistance increases protection time
Solution Approach 1:
By stacking semiconducting layers vertically and creating a vertical current path, the device achieves lower dynamic resistance. This vertical configuration allows faster discharge of electrostatic energy, reducing the time the protection device remains in the conducting state and enabling quicker return to the blocking state.
3Reliability
If laterally integrated devices are used, then ESD protection is achieved, but increased wafer or die area consumption occurs
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple semiconducting layers (n-type 305, p-type 310, n-type 315) above each other, enabling ESD protection functionality within a smaller lateral footprint. This vertical integration significantly reduces the required wafer or die area compared to conventional lateral thyristor structures.
4Reliability
If electrical bypass is added to reduce resistance, then holding current increases, but device complexity increases
Solution Approach 1:
The electrical bypass structure is merged with the vertical thyristor stack by integrating the bypass path within the same vertical architecture. The bypass connects adjacent like-type layers (n-type to n-type or p-type to p-type) through the vertical stack, providing holding current stabilization without requiring separate external bypass circuits, thus minimizing additional complexity.
Data Source
AI summary
A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.