Vertical Thyristor Memory Cell Isolation Using Air Gaps
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Solution Overview
Problem
As semiconductor thyristor memory cell sizes decrease, the isolation regions between adjoining cells become smaller, leading to capacitive coupling and interference between neighboring cells, which can degrade memory array performance and change the state of thyristors.
Innovation Solution
The introduction of air gaps or conducting rods within trench isolation regions in vertical thyristor memory cells, surrounded by insulating material, to enhance electrical isolation and prevent cell interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thyristor memory cell size is reduced to increase density, then storage capacity improves, but isolation between cells deteriorates leading to capacitive coupling and interference
Solution Approach 1:
An air gap is introduced as an intermediary material in the isolation trench between adjacent thyristor cells. This air gap acts as a mediator with very low dielectric constant (approximately 1.0), significantly reducing capacitive coupling between cells while allowing the cells to be closely spaced for high density.
Solution Approach 2:
The dielectric parameter of the isolation medium is changed from conventional solid insulators (with dielectric constants of 3.9-11.9) to air (dielectric constant ≈ 1.0). This parameter change reduces the capacitive coupling coefficient between adjacent cells, enabling closer cell spacing without increasing interference.
2Area of stationary object
If isolation region size is reduced to accommodate smaller cells, then cell density improves, but electrical isolation performance deteriorates
Solution Approach 1:
The dielectric constant parameter of the isolation material is changed from high values (solid insulators) to the minimum possible value (air ≈ 1.0). This allows the isolation region to be smaller in area while maintaining or even improving electrical isolation performance, as the capacitive coupling is reduced by the low dielectric constant rather than requiring larger physical dimensions.
Solution Approach 2:
The air gap isolation structure can be replicated across the entire memory array in a systematic manner. Each isolation trench between cells is filled with air (or left as void space), creating a consistent low-dielectric environment throughout the array that maintains isolation performance across all cell pairs.
3Object-affected harmful factors
If air gap isolation is used to reduce interference, then cell isolation improves, but manufacturing complexity increases
Solution Approach 1:
Instead of adding complex isolation structures, the solution extracts or removes material to create air gaps. The isolation trenches are etched and left partially empty, allowing air to provide the isolation function. This 'taking out' approach is simpler than adding complex insulating structures, as it relies on the natural properties of air rather than requiring additional material deposition and patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces cross-coupling between neighboring cells, improving memory array stability and allowing for closer packing of thyristor cells without electrical interference, with air gaps providing the lowest dielectric constant and embedded conductors terminating or bending electric field lines for reduced interference.
Implementation Method 1
air gaps providing the lowest dielectric constant and embedded conductors terminating or bending electric field lines for reduced interference
Implementation Method 2
embedded conductors terminating or bending electric field lines for reduced interference
Data Source
AI summary
Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.