Vertical Tin Monoxide Channels for High-Current Thin Film Transistors

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Solution Overview

Problem

Existing thin film transistors using semiconductor oxides face challenges in maximizing hole mobility and channel width, leading to suboptimal performance due to limitations in channel configuration and material properties.

Innovation Solution

The development of semiconductor structures with vertical channels made of tin monoxide, arranged in a multi-layered atomic structure, allowing for high hole mobility in the vertical direction and increased channel width without occupying a large area, utilizing a metal gate to surround the channels and controlling gate length effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If horizontal channels are used in thin film transistors, then the device area is reduced, but hole mobility and charge carrier transmission efficiency are limited

Engineering Contradiction:
Improvehole mobilityVSAvoidcharge carrier transmission efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent transitions from conventional horizontal channel configuration to vertical channel configuration, changing the spatial dimension of charge carrier transport. This dimensional change enables exploitation of the highly anisotropic hole mobility in tin monoxide, where vertical mobility is significantly higher than horizontal mobility, thereby resolving the contradiction between limited hole mobility and charge carrier transmission efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the crystallographic orientation parameter of the tin monoxide channel from horizontal to vertical alignment. By controlling the atomic layer stacking direction and channel orientation, the patent accesses the high-mobility vertical transport pathway inherent in the tin monoxide crystal structure, transforming the material's effective mobility parameter for optimal performance.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If channel width is increased to improve current flow, then the transistor area occupies more space

Engineering Contradiction:
Improvetotal current flowVSAvoidtransistor area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent moves the channel extension from the lateral plane to the vertical dimension. By stacking multiple atomic layers vertically to create the channel length and utilizing vertical charge transport, the patent achieves large effective channel width and high total current flow without increasing the lateral footprint of the transistor, thus resolving the area-current flow contradiction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs a multi-layered atomic structure with vertical channels that create a porous-like three-dimensional architecture. This vertical stacking of conducting oxide layers with embedded semiconductor oxide channels enables multiple parallel charge transport pathways within a compact volume, increasing total current capacity without lateral area expansion.

Inventive Principle:
Principle #31Porous materials

Data Source

PatentUS20250359187A1Semiconductor structure having vertical channels and method for manufacturing the same
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250359187A1 patent drawing
  • US20250359187A1 patent drawing
  • US20250359187A1 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes: depositing atomic layers of tin monoxide along a vertical direction; patterning the atomic layers of tin monoxide into a channel unit; forming a first conducting oxide unit that is connected to the channel unit; forming a second conducting oxide unit that is connected to the channel unit and that is spaced apart from the first conducting oxide unit so as to permit charge carriers to be transmitted between the first conducting oxide unit and the second conducting oxide unit through the patterned atomic layers in the channel unit along the vertical direction; forming a gate dielectric over the channel unit, the first and second conducting oxide units; forming a metal gate over the gate dielectric; recessing the metal gate to expose the gate dielectric; and partially removing the gate dielectric to expose at least the first conducting oxide unit.