Vertical TIR Mirror in Silicon Photonic Circuits
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Solution Overview
Problem
Silicon photonic circuits face challenges in routing light vertically for efficient coupling with Ge-based photodetectors and require costly and time-consuming wafer singulation and polishing for optical testing.
Innovation Solution
A vertical total internal reflection (TIR) mirror is created using crystallographic silicon etching to reflect light normal to the wafer surface, enabling efficient coupling and wafer-level optical testing by forming a re-entrant profile with 54° facets in the silicon layer, allowing for smooth and efficient light reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar photodetectors are used with Ge grown on top of Si waveguide, then photodetector integration is achieved, but the photodetector size becomes large due to inefficient optical coupling
Solution Approach 1:
The patent introduces a vertical dimension by creating a re-entrant profile with a (111) crystal plane facet that reflects light upward at a 54-degree angle. This vertical light reflection path enables compact planar photodetectors to efficiently couple with the waveguide, eliminating the need for large detector areas while maintaining high coupling efficiency through the vertically-oriented optical path.
2Area of moving object
If trench sidewall photodetectors are used with vertical facet, then photodetector size is reduced, but the facet smoothness and epitaxial growth become difficult to achieve
Solution Approach 1:
The patent changes the crystallographic orientation parameter by utilizing the silicon (111) plane, which naturally forms smooth facets at a 54-degree angle to the surface. This crystallographic parameter change enables the formation of smooth vertical reflection surfaces through standard etching processes, avoiding the manufacturing difficulties associated with arbitrary vertical facets while maintaining compact photodetector geometry.
3Ease of operation
If wafer singulation and edge polishing are performed for optical testing, then optical testing can be conducted, but the process becomes expensive and time consuming
Solution Approach 1:
The patent replaces the mechanical process of wafer singulation and edge polishing with an optical solution—the vertical TIR mirror that enables light to be coupled into and out of the waveguide through the wafer surface. This substitution eliminates the need for mechanical wafer processing steps, allowing optical testing to be performed directly on intact wafers, thereby reducing both time and cost while maintaining testing capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient light coupling and reduces development times and testing costs by enabling rapid and inexpensive wafer-level optical testing, facilitating the integration of planar silicon waveguides with Ge-based photodetectors without the need for costly singulation and polishing.
Implementation Method 1
A vertical total internal reflection (TIR) mirror is created using crystallographic silicon etching to reflect light normal to the wafer surface
Data Source
AI summary
A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.