Vertical TMD Transistor Channels for Higher On-State Current
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Solution Overview
Problem
Transition metal dichalcogenide (TMD) materials in semiconductor devices face challenges with poor 'on' state current due to low contact resistivity and channel mobility, limiting their effectiveness in field effect transistor (FET) structures.
Innovation Solution
The use of vertical TMD nanosheets in semiconductor devices, where TMD carriers are epitaxially grown in channels within a gate structure, enabling current flow between metal contacts, and the application of voltage activates these carriers for efficient current transmission across PFET and NFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If TMD materials are used in transistor channels, then device downscaling is achieved, but on-state current deteriorates due to low contact resistivity
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor channels to vertical (3D) TMD nanosheet channels. This dimensional change allows the channel to extend vertically through the gate structure, increasing the effective channel length without increasing the device footprint, thereby maintaining device downscaling while improving contact resistivity and on-state current through optimized vertical transport paths
Solution Approach 2:
The patent employs composite material structures including TMD nanosheets integrated with metal contacts, gate dielectrics, and doped semiconductor regions. The vertical nanosheet configuration creates a composite architecture where TMD materials form the channel core, surrounded by engineered interfaces with metal contacts and gate structures, optimizing both electrical contact and channel transport properties
2Length of moving object
If TMD materials are used in transistor channels, then device downscaling is achieved, but channel mobility deteriorates
Solution Approach 1:
The vertical orientation of TMD nanosheets creates a three-dimensional channel architecture where charge carriers transport vertically through the gate structure. This vertical transport path, enabled by the nanosheet configuration, improves channel mobility by reducing scattering at horizontal interfaces and optimizing the electric field distribution along the vertical channel length
Solution Approach 2:
The patent implements localized quality optimization through doped regions positioned at specific locations within the vertical channel structure. The gate structure includes first and second doped regions that create localized electric field enhancements and carrier concentration gradients, improving mobility in critical transport regions while maintaining overall device scaling
3Ease of manufacture
If conventional transistor designs are used, then manufacturing simplicity is maintained, but polarity versatility is limited
Solution Approach 1:
The vertical TMD nanosheet channel architecture serves as a universal platform that can support both n-type and p-type transistor operations. The same basic vertical channel structure can be adapted for different polarities by modifying the gate electrode configuration and doping profiles, enabling a single manufacturing platform to produce multiple device types with different polarities
Solution Approach 2:
The patent achieves polarity versatility through parameter changes in the vertical channel structure, specifically by adjusting gate voltage polarity, metal contact work functions, and doped region concentrations. These parameter modifications allow the same vertical TMD nanosheet channel to operate in both enhancement and depletion modes for n-type and p-type devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the current flow and mobility in TMD-based semiconductor devices, improving their performance by activating TMD carriers through voltage application, thereby addressing the limitations of traditional TMD materials in FET structures.
Implementation Method 1
activated by gate voltage to enable current flow across contacts
Implementation Method 2
the use of epitaxial growth to maintain crystalline integrity
Data Source
AI summary
A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.