Vertical TMD Ring Transistor Structure for Short-Channel Scaling
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes to increase integration density, challenges arise in forming transistors with effective scaling capabilities and minimizing the short-channel effect while maintaining low sub-threshold swing.
Innovation Solution
A three-dimensional transistor is formed using a two-dimensional semiconductor material, specifically a Transition Metal Dichalcogenide (TMD) layer on the sidewalls of a dielectric fin, with a gate stack and source/drain contact plugs designed to maximize contact area and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then integration density is improved, but short-channel effect increases and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to three-dimensional (3D) vertical architecture. The channel is formed vertically along the sidewalls of dielectric fins rather than horizontally, allowing current flow in the vertical direction while gate control is exerted from the top. This dimensional change enables continued scaling of channel length without proportionally increasing short-channel effects, as the vertical geometry provides better electrostatic control over the channel region.
Solution Approach 2:
The patent implements a nested structure where the two-dimensional semiconductor material is conformally deposited on the sidewalls of the dielectric fin, creating a vertical channel that is nested within the fin structure. The gate stack is then formed over this nested channel structure, creating a hierarchical arrangement that maximizes gate control while minimizing short-channel effects.
2Productivity
If channel length is scaled down to improve integration density, then integration density is improved, but sub-threshold swing increases
Solution Approach 1:
By transitioning to vertical channel architecture, the patent achieves better gate control over the channel despite reduced channel length. The vertical geometry allows the gate to exert stronger electrostatic control, maintaining lower sub-threshold swing values even as channel length is scaled down to increase integration density.
Solution Approach 2:
The patent employs two-dimensional semiconductor materials (such as transition metal dichalcogenides) that exhibit superior electrostatic properties compared to conventional bulk semiconductors. These 2D materials enable effective gate control in vertical channel structures, maintaining low sub-threshold swing while allowing aggressive channel length scaling.
3Reliability
If contact area is increased to reduce contact resistance, then contact resistance is reduced, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension to increase contact area without expanding the planar footprint. Source and drain contact plugs are formed that extend vertically to contact the vertical channel structure along its length, providing extended contact area in the vertical direction while maintaining a compact planar device area.
Solution Approach 2:
The contact plugs are nested within trenches that extend vertically through the device structure, allowing the contacts to reach the vertical channel structure without requiring additional planar space. This nested arrangement maximizes contact area while minimizing the device's planar footprint.
Data Source
AI summary
A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.