Vertical TRAM for High Integration and Low Power
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Solution Overview
Problem
Existing flash memory technologies face challenges in achieving high integration and operational reliability due to high power consumption, limited flexibility, and structural limitations, particularly in wearable devices and neuromorphic applications, where they require two electrodes and have low operation reliability and high power loss.
Innovation Solution
A vertical tunneling random access memory (TRAM) design with a first electrode, a second electrode vertically spaced from the first, a floating gate, a tunneling insulating layer, and a barrier insulating layer, where the semiconductor pattern extends from the second electrode to the first, allowing for charge accumulation and reduced driving voltage, enabling high integration and reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a horizontal tunneling random access memory structure is used, then operational reliability is improved, but device integration density deteriorates
Solution Approach 1:
The patent transitions from a horizontal two-dimensional layout to a vertical three-dimensional structure. The source and drain electrodes are positioned vertically above each other rather than horizontally adjacent, enabling charge confinement in the floating gate without requiring large horizontal spacing. This dimensional change resolves the contradiction by achieving both high reliability through proper charge confinement and high integration density through vertical stacking.
2Reliability
If the source and drain are separated by 10 μm in horizontal TRAM, then charge confinement is improved, but driving voltage increases
Solution Approach 1:
The patent repositions the source and drain electrodes from horizontal separation to vertical separation. This allows charge confinement to be achieved through vertical field effects rather than horizontal distance, dramatically reducing the required electrode separation from 10 μm to much smaller dimensions. The vertical configuration maintains effective charge confinement while enabling operation at lower driving voltages suitable for integrated circuits.
3Area of stationary object
If flash memory is integrated in vertical direction, then integration density is improved, but flexibility and stretchability deteriorate
Solution Approach 1:
The patent employs thin-film layer structures for the vertical TRAM device, including thin insulating layers and conductive layers that can be deposited on flexible substrates. This thin-film approach enables vertical integration while maintaining the flexibility and stretchability required for wearable applications, resolving the contradiction between high integration density and mechanical flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical TRAM achieves reduced driving voltage and improved integration by stacking semiconductor devices in a 3D configuration, enhancing operational reliability and enabling the use in wearable devices with lower power consumption.
Implementation Method 1
a tunneling insulating layer disposed between the first electrode and the floating gate
Implementation Method 2
a barrier insulating layer disposed between the floating gate and the second electrode
Implementation Method 3
a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode
Data Source
AI summary
The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.