Vertical Transfer Gate Transistor for Image Lag Prevention
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Solution Overview
Problem
High integration degree image sensors face challenges in preventing image lag and maintaining full-well capacity due to reduced photodiode size and non-uniform doping concentrations in transfer gate transistors, leading to increased electrical resistance and operational defects.
Innovation Solution
The image sensor incorporates a vertical transfer gate transistor with a recessed structure and a cavity on its upper surface, featuring a gate conductive pattern with uniform doping concentration along the substrate surface profile, including a polysilicon layer doped with impurities, which enhances charge transfer efficiency and reduces operational failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the photodiode size is reduced to increase integration degree, then the number of pixels increases, but the full-well capacity decreases and image lag increases
Solution Approach 1:
The transfer gate is changed from a planar structure to a vertical structure extending in the depth direction of the substrate. This dimensional change allows the transfer gate to span across multiple photodiodes vertically arranged, enabling efficient charge transfer even when photodiode surface area is reduced, thus preventing image lag while maintaining high integration degree
Solution Approach 2:
The vertical transfer gate structure is nested within the substrate depth, utilizing the third dimension (depth) to accommodate the gate structure without increasing the surface footprint. This allows the transfer gate to service multiple photodiodes vertically stacked, maintaining full-well capacity while achieving high pixel density
2Ease of manufacture
If the transfer gate transistor uses conventional doping methods, then the manufacturing process is simple, but the doping concentration is non-uniform causing increased electrical resistance
Solution Approach 1:
The doping process is tailored to the specific geometry of the vertical transfer gate, applying doping conditions that ensure uniform concentration along the gate's extended structure. The doping concentration is optimized locally at different positions (surface vs. depth) to compensate for the vertical extension, achieving uniform electrical properties throughout the gate structure
Solution Approach 2:
The doping parameters (concentration, depth, duration) are adjusted to match the vertical geometry of the transfer gate. By changing the doping parameters from conventional planar values to vertical-optimized values, uniform doping concentration is achieved throughout the extended gate structure, reducing electrical resistance while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the full-well capacity and drive range of the image sensor by ensuring uniform doping concentration, minimizing image lag, and simplifying the manufacturing process without additional steps, thereby increasing operational reliability.
Implementation Method 1
a gate conductive pattern, including polysilicon doped with impurities, on the gate insulation pattern along the surface profile of the substrate having the recess
Implementation Method 2
An image sensor includes a semiconductor device for transforming optical image signals into electric signals
Data Source
AI summary
In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.