Vertically Oriented Transformer Shielding Structure
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Solution Overview
Problem
Conventional semiconductor IC components, such as transformers and inductors, face issues like excess space consumption, poor device performance, inadequate shielding, and high fabrication costs due to inefficiencies in chip area utilization and increased power losses from eddy currents.
Innovation Solution
The development of vertically-oriented transformers and inductors with variable metal width coils and interconnect structures that reduce eddy current losses and improve coupling factors, allowing for more efficient chip area use and higher impedance transformation ratios, along with the implementation of shielding structures to minimize noise and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar electronic components are used, then fabrication is simpler, but chip area consumption is excessive
Solution Approach 1:
The patent transitions from conventional planar (2D) electronic components to vertically-oriented (3D) components. The coils are configured with vertical windings extending through multiple metal layers, transforming the component geometry from flat to three-dimensional. This dimensional change enables significantly higher functional density on the chip area while maintaining compatibility with standard semiconductor fabrication processes through the use of vertical vias and stacked metal interconnects.
2Reliability
If conventional planar components are used, then fabrication process is simpler, but device performance is poor
Solution Approach 1:
The vertically-oriented configuration with coils winding through multiple metal layers improves device performance by increasing the effective winding area and coupling factor while reducing parasitic effects. The three-dimensional arrangement allows for better magnetic field confinement and improved impedance transformation ratios, directly enhancing transformer and inductor performance metrics.
Solution Approach 2:
The patent implements nested structures where multiple coils are stacked vertically through different metal layers, with each coil nested within the vertical space occupied by others. This nesting approach maximizes the use of available chip volume, allowing multiple functional elements to occupy the same footprint area while maintaining electrical isolation through dielectric layers and via structures.
3Object-affected harmful factors
If conventional components are used, then shielding is inadequate, but adding shielding increases fabrication complexity
Solution Approach 1:
The vertically-oriented interconnect structure serves multiple functions simultaneously: it provides electrical connections between layers, acts as shielding against electromagnetic interference, and enables the primary functional components (transformers and inductors). The metal layers and via structures that are necessary for the vertical component configuration also function as inherent shielding elements, eliminating the need for separate dedicated shielding structures and reducing overall fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced chip area consumption, lower substrate losses, improved high-frequency performance, and enhanced impedance transformation capabilities, while also providing effective shielding against noise and interference.
Implementation Method 1
a first coil and a second coil that each have a winding orientation defined at least in part by a third axis that is perpendicular to the surface of the substrate
Implementation Method 2
conventional electronic components formed on an IC may face shortcomings such as excess space consumption, poor device performance, inadequate shielding, and high fabrication costs
Data Source
AI summary
The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.