Vertical Transistor With 2D Material Channel And Gate-All-Around Structure
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Solution Overview
Problem
Current vertical transistor devices face challenges in miniaturization and performance enhancement due to limitations in materials used in their channel regions, particularly in integrating two-dimensional (2D) materials effectively for improved electronic, thermal, and mechanical properties.
Innovation Solution
The integration of at least one layer of 2D material in the channel region of vertical transistor devices, with a gate structure surrounding the 2D material layers, and a vertically stacked arrangement of these layers with rotated periodic crystallographic patterns to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional materials are used in the channel region, then the device structure is simple and easy to manufacture, but the electronic performance and charge carrier mobility are limited
Solution Approach 1:
The patent uses two-dimensional materials (such as graphene, transition metal dichalcogenides) as composite channel structures to replace conventional semiconductor materials. These 2D materials provide superior electronic performance, high charge carrier mobility, and excellent gate control while maintaining compatibility with existing semiconductor manufacturing processes through established deposition and patterning techniques.
Solution Approach 2:
The patent changes the material parameters of the channel region by introducing 2D materials with unique electronic band structures, atomic thickness, and high surface-to-volume ratios. This fundamentally alters the electrical characteristics, enabling enhanced charge carrier mobility and improved electrostatic control without requiring complete process overhaul.
2Area of stationary object
If the transistor size is reduced, then the chip area utilization improves, but short channel effects increase and performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D channel configurations using multiple layers of 2D materials. This vertical stacking increases the effective channel width without increasing the lateral footprint, achieving higher current drive capability and improved gate control while maintaining compact chip area utilization.
Solution Approach 2:
The patent implements gate-all-around structures that completely surround the vertical channel stacks, with multiple gate layers nested around multiple channel layers. This nested configuration provides maximum electrostatic control over the channel, effectively suppressing short channel effects even at reduced device dimensions.
3Productivity
If more circuit elements are integrated on restricted chip area, then the productivity increases, but the device size reduction leads to increased manufacturing complexity
Solution Approach 1:
The patent divides the channel structure into multiple discrete 2D material layers stacked vertically, with each layer serving as an independent conduction path. This segmentation allows for scalable integration where multiple devices can be stacked vertically or placed in close proximity, increasing circuit element density while maintaining manageable individual device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves charge carrier mobility, gate control, and reduces short channel effects, leading to enhanced performance capabilities while maintaining mechanical strength and conductivity.
Implementation Method 1
Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region
Implementation Method 2
single-sheet 2D materials may possess many beneficial properties, such as high mechanical strength, high electronic and thermal conductivity
Implementation Method 3
single-sheet 2D materials may possess many beneficial properties, such as high mechanical strength, high electronic and thermal conductivity
Data Source
AI summary
One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.