Vertical Transistor with 2D Source-Drain Regions
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Solution Overview
Problem
Current vertical transistor devices face challenges in miniaturization and performance enhancement due to limitations in materials used for source/drain regions, as they do not fully leverage the unique properties of two-dimensional (2D) materials.
Innovation Solution
The development of vertical transistor devices with source/drain regions comprising at least one layer of 2D material, where the 2D material layers are strategically positioned and rotated to optimize electrical performance, and integrated into a gate-all-around structure using known manufacturing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional materials are used for source/drain regions in vertical transistor devices, then manufacturing processes are well-established and simple, but charge carrier mobility and electrical performance are limited
Solution Approach 1:
The patent employs two-dimensional materials (such as graphene, transition metal dichalcogenides, or other 2D materials) for the source/drain regions instead of conventional bulk semiconductor materials. This composite material approach enables superior charge carrier mobility and electrical performance while maintaining compatibility with existing vertical transistor device architectures and manufacturing processes
Solution Approach 2:
The patent changes the material parameter from conventional bulk semiconductors to two-dimensional materials with unique electronic properties. This parameter change in material dimensionality and structure enables improved charge carrier mobility, reduced scattering effects, and enhanced electrical performance in the source/drain regions of vertical transistor devices
2Productivity
If device size is reduced to increase circuit density, then more transistors can be placed on chip area, but short channel effects and gate control deteriorate
Solution Approach 1:
The patent transitions from planar transistor geometry to a vertical transistor architecture where the channel extends in the vertical dimension rather than laterally. This dimensional change allows the gate to wrap around the channel in a gate-all-around configuration, providing superior electrostatic control and reducing short channel effects even as device dimensions are scaled down to increase circuit density
Solution Approach 2:
The gate structure is positioned to completely surround the channel region in a gate-all-around configuration, with the gate electrode wrapping around the channel from all sides. This nested arrangement provides maximum gate control over the channel, effectively suppressing short channel effects and enabling continued scaling for higher circuit density
3Reliability
If 2D material layers are rotated relative to each other, then electrical performance and charge carrier mobility are optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different rotational orientations to different 2D material layers in the stacked structure. By optimizing the local orientation of each layer relative to its neighbors, the device achieves enhanced electrical performance and charge carrier mobility through improved band structure alignment and reduced scattering, while the overall structure remains compatible with manufacturing capabilities
Data Source
AI summary
One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.