Vertical Transistor Air Gap Reduces Gate Capacitance
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Solution Overview
Problem
Conventional vertical transistors face issues such as gouging during fin structure etching, variability in spacer and gate alignment, and dopant diffusion leading to increased gate capacitance and non-controlled junctions.
Innovation Solution
A vertical transistor design featuring a fin structure with an air gap between the bottom source/drain region and the gate structure, where the bottom S/D region is formed by epitaxial growth with a merged first and second epitaxial layer, and an insulating layer with a cavity, allowing the gate structure to extend across and have a width less than the cavity, thereby reducing gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bottom S/D region is formed in direct contact with the gate structure, then the manufacturing process is simpler, but the gate capacitance increases
Solution Approach 1:
The patent extracts the harmful capacitive coupling between the bottom S/D region and gate structure by removing the direct physical contact and replacing it with an air gap. This separation eliminates the unwanted electrical interaction while maintaining the necessary functional connections through other means.
Solution Approach 2:
The air gap acts as an intermediary medium between the bottom S/D region and gate structure. This intermediate space provides electrical isolation to reduce capacitance while allowing the structure to maintain its functional integrity through the fin channel and other conductive paths.
2Productivity
If the fin structure is etched without protective measures, then the manufacturing process is faster, but gouging occurs during etching
Solution Approach 1:
The patent applies preliminary protective action by forming the air gap structure before the etching process. This pre-formed air gap acts as a protective barrier that prevents gouging during subsequent etching operations while allowing the process to proceed at high speed.
3Ease of manufacture
If spacer and gate alignment is performed without precise control, then the manufacturing process is simpler, but variability in alignment increases
Solution Approach 1:
The air gap structure serves as a self-aligning feature that guides the positioning of the gate relative to the bottom S/D region. The physical presence of the air gap provides natural alignment references that reduce variability without requiring complex alignment procedures.
4Ease of manufacture
If dopant diffusion is not controlled, then the manufacturing process is simpler, but junction position control deteriorates
Solution Approach 1:
The patent extracts the source of unwanted dopant diffusion by removing direct contact between the bottom S/D region and gate structure. The air gap prevents dopant migration paths that would otherwise occur through direct interfaces, thereby maintaining precise junction position control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a well-controlled junction position and reduced gate capacitance, enhancing the performance of the vertical transistor, particularly in memory devices.
Implementation Method 1
a bottom source/drain (S/D) region formed on the fin structure, such that an air gap is formed between the bottom S/D region and the gate structure. The bottom S/D region includes a first epitaxial layer which is grown from a bottom portion of the fin structure, a second epitaxial layer which is grown from a surface of the substrate, and merged with the first epitaxial layer
Data Source
AI summary
A method of forming a vertical transistor includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a bottom source/drain (S/D) region on the fin structure, such that an air gap is formed between the bottom S/D region and the gate structure.