Vertical Transistor Air Gap Reduces Gate Capacitance
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Solution Overview
Problem
Conventional vertical transistors face issues such as gouging during etching, variability in spacer and gate alignment, and increased gate capacitance due to dopant diffusion, leading to non-controlled junctions and higher capacitance.
Innovation Solution
A vertical transistor design featuring a fin structure with an air gap between the bottom source/drain region and the gate structure, where the bottom S/D region is formed by epitaxially growing layers from both the fin and substrate, and an insulating layer with a cavity, allowing the gate to extend across and have a width less than the cavity, thereby reducing gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bottom S/D region is formed in direct contact with the gate structure, then the manufacturing process is simpler, but the gate capacitance increases
Solution Approach 1:
The patent extracts the harmful capacitive coupling between the bottom S/D region and the gate structure by removing the direct physical contact and replacing it with an air gap. This separation eliminates the parasitic capacitance while maintaining the electrical functionality of the device.
Solution Approach 2:
The air gap acts as an intermediary medium between the bottom S/D region and the gate structure. This intermediate space provides electrical isolation to reduce capacitance while still allowing the structural integrity and functional operation of the transistor to be maintained.
2Ease of manufacture
If conventional etching is used to form fin structures, then the process is straightforward, but gouging occurs during etching
Solution Approach 1:
The patent applies preliminary protective actions by forming a sacrificial layer and using carefully controlled etching conditions before the main etching process. This preliminary preparation prevents gouging by establishing a protective framework that guides the etching process and prevents excessive material removal.
3Ease of manufacture
If dopant diffusion is allowed during processing, then the junction formation is simpler, but alignment variability increases
Solution Approach 1:
The patent extracts the problematic dopant diffusion by removing the continuous material contact between regions. The air gap prevents dopant atoms from migrating between the bottom S/D region and the gate structure, thereby eliminating alignment variability caused by uncontrolled diffusion while maintaining simplified processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a well-controlled junction position and reduced gate capacitance, improving the performance of vertical transistors by minimizing dopant diffusion and alignment variability.
Implementation Method 1
an air gap is formed between the bottom S/D region and the gate structure
Implementation Method 2
a first epitaxial layer which is grown from a bottom portion of the fin structure, a second epitaxial layer which is grown from a surface of the substrate
Data Source
AI summary
A semiconductor device includes a source/drain (S/D) region, a fin structure formed on the S/D region, and a gate structure formed on the fin structure so that a space is formed between the S/D region and the gate structure.