Vertical Transistor Sidewall Gate Air Gaps Reduce Leakage
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Solution Overview
Problem
As process geometries shrink in non-volatile memory devices, controlling and minimizing leakage currents in cross-point memory arrays without isolation elements becomes a significant challenge, especially due to varying biasing voltage and temperature conditions.
Innovation Solution
A monolithic three-dimensional memory array is formed with vertically-oriented transistors having sidewall gates and an air gap chamber between them, which reduces capacitive coupling and leakage currents by incorporating air gaps that separate bit line select transistors, thereby improving transistor speed and reducing cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If process geometries are shrunk to reduce cost per bit, then manufacturing cost decreases, but leakage current control becomes more difficult
Solution Approach 1:
An air gap is introduced as an intermediary structure between adjacent bit line select transistors. This air gap acts as a mediator that reduces capacitive coupling between the transistors, thereby minimizing leakage current and cross-talk without requiring changes to the transistor geometry itself. The air gap serves as a physical separator that maintains electrical isolation while allowing continued scaling of the memory array.
2Reliability
If air gaps are introduced to reduce capacitive coupling, then leakage current and cross-talk are minimized, but device structure becomes more complex
Solution Approach 1:
The air gap structure is formed by removing (extracting) a sacrificial material layer between the bit line select transistors. This extraction process creates the air gap chamber that provides electrical isolation. By taking out the sacrificial material, the patent achieves leakage current control without adding complex structural elements, as the air gap is essentially a void space rather than a added component.
3Productivity
If vertically-oriented transistors with sidewall gates are used, then transistor density increases, but capacitive coupling between adjacent transistors increases
Solution Approach 1:
The air gap chamber segments the memory array by physically dividing it into separate regions. This segmentation isolates adjacent bit line select transistors, preventing capacitive coupling between them. By segmenting the continuous structure into discrete, isolated units, the patent maintains high transistor density while eliminating the harmful capacitive effects that would otherwise result from close spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes leakage currents and enhances the speed of bit line select transistors, addressing the design and process challenges in scaling down non-volatile memory devices by utilizing air gaps to reduce capacitive coupling and cross-talk.
Implementation Method 1
reduces capacitive coupling and leakage currents by incorporating air gaps that separate bit line select transistors
Data Source
AI summary
A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.