Vertical Transistor Array Layout for Smaller Memory Cell Footprint
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Solution Overview
Problem
Conventional transistors, such as planar and Buried Channel Array Transistors, have source and drain locations on horizontal sides of the gate, leading to increased area occupancy and complex circuit wiring, making manufacturing difficult, especially in memory devices like DRAM.
Innovation Solution
A method to manufacture a transistor array where the source and drain are positioned at opposite ends of a channel region, allowing for a vertical orientation, reducing the transistor's area footprint and simplifying circuit layout by enabling different structures to be connected on opposite surfaces of the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source and drain are located on horizontal sides of gate, then transistor can be formed using conventional planar structure, but transistor area becomes larger
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional vertical structure. The channel is formed vertically through the substrate with source and drain regions positioned at different depths, allowing the gate to wrap around the channel in a cylindrical or planar configuration. This dimensional change reduces the footprint area while maintaining the essential transistor functionality.
2Reliability
If source and drain occupy different horizontal positions, then transistor can function properly, but manufacturing difficulty increases
Solution Approach 1:
The patent employs preliminary patterning steps where the channel structure is formed first through selective etching or deposition, followed by sequential formation of source and drain regions. The gate structure is then deposited to wrap around or cover the channel, ensuring proper spatial relationships are established before final processing steps.
Solution Approach 2:
The vertical configuration allows source and drain to be positioned at different depths along the vertical axis rather than requiring precise lateral positioning. This dimensional reorganization simplifies the manufacturing process by enabling standard planar processing techniques to be applied while achieving three-dimensional functionality.
Data Source
AI summary
The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars is located at a corresponding grid point of the grid-like etched trench and has a first preset thickness smaller than an initial thickness of the wafer; and the first direction is a thickness direction of the wafer and is perpendicular to the first surface. An insulating material is deposited in the grid-like etched trench to form an insulating layer.