Vertical Transistor Atomic Layer Gate Length
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Solution Overview
Problem
Traditional planar field effect transistors face challenges in scaling due to lithographic constraints, limiting further performance improvements and increasing dimensions, while maintaining reliability.
Innovation Solution
The development of vertical field effect transistors with ultrathin two-dimensional materials for the gate, allowing for reduced gate length that is determined by the thickness of the gate material, and a vertical architecture that overcomes traditional scaling limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional planar FET scaling is used to increase operating frequency, then transistor performance improves, but device dimensions increase and reliability degrades
Solution Approach 1:
The patent transitions from a planar (2D) transistor architecture to a vertical (3D) architecture. The channel is configured vertically with the gate wrapping around it, allowing current to flow vertically through the channel while the gate controls it from the sides. This dimensional change enables continued frequency improvement without the same scaling penalties as planar devices.
2Speed
If gate length is reduced to improve performance, then operating frequency increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the defining parameter for gate length from a lateral dimension (controlled by lithography) to a vertical dimension (controlled by thin film deposition thickness). The gate length is now determined by the thickness of the gate dielectric and channel layer, which can be controlled with atomic-layer precision using ALD or other deposition techniques, bypassing lithographic resolution limits.
3Productivity
If device dimensions are reduced to increase density, then device packing increases, but parasitic components increase
Solution Approach 1:
By moving to a vertical architecture, the patent achieves higher device density by stacking components vertically rather than packing them laterally. This vertical integration reduces the lateral footprint and associated parasitic interconnect lengths, while the wrapped gate configuration minimizes gate-to-source/drain parasitic capacitances by optimizing the electric field distribution.
Data Source
AI summary
A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.