Vertical Transistor Back-Side Interconnect Layout for Sub-5nm Scaling
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Solution Overview
Problem
Conventional semiconductor fabrication techniques are reaching limits in scaling down devices, such as gate lengths, and there is a need for new structural features to achieve higher density and performance in integrated circuit devices, particularly for vertical transport FETs (VTFETs) to support further miniaturization beyond 5 nanometers.
Innovation Solution
The development of vertical transport transistor devices with back side interconnects, which involve forming a semiconductor structure with a vertical transistor, contacts to source/drain regions, and interconnect structures that connect these contacts across the device, allowing for efficient wiring of bottom source/drain regions to front side signaling using back side local interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional semiconductor fabrication techniques are used, then manufacturing simplicity is maintained, but device scaling below 5 nanometers becomes difficult
Solution Approach 1:
The patent transitions from planar 2D transistors to vertical 3D transistors, enabling continued scaling of gate length by exploiting the vertical dimension. The vertical channel extends perpendicular to the substrate surface, allowing smaller gate lengths without proportionally increasing fabrication complexity, as the vertical architecture naturally accommodates advanced node dimensions.
Solution Approach 2:
The device is segmented into distinct functional regions including the vertical channel, gate structures, source/drain regions, and interconnect layers. This segmentation allows each component to be optimized and fabricated using specialized processes, enabling precise control at sub-5nm scales while managing overall fabrication complexity through modular construction.
2Area of stationary object
If device size is reduced for miniaturization, then integration density improves, but wiring and interconnect complexity increases
Solution Approach 1:
The vertical transistor architecture moves critical functions into the third dimension, allowing interconnects to access source/drain regions from both the front (top) and back (bottom) of the device. This dual-sided access reduces the need for lengthy lateral interconnect paths, decreasing interconnect complexity while maintaining high integration density on the chip area.
Solution Approach 2:
The patent utilizes back-side interconnects, inverting the conventional approach where all interconnects are accessed from the front side. By routing interconnects through the substrate to contact the back side of the vertical transistor, the design reduces lateral interconnect length and enables more efficient wiring schemes that decrease overall interconnect complexity.
3Productivity
If vertical transport FETs are implemented, then device density and performance improve, but manufacturing processes become more complex
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming the vertical channel and gate structures, creating source/drain regions, depositing front-side interconnects, and adding back-side interconnects. This segmentation of the fabrication process into modular steps makes the complex vertical FET manufacturing more manageable and scalable, enabling high device density while controlling process complexity through systematic breakdown of operations.
4Adaptability or versatility
If multiple signal accesses are accommodated in a single dummy fin structure, then integration capability increases, but device structure becomes more complex
Solution Approach 1:
The dummy fin structure is designed to serve multiple functions: it provides mechanical support, enables back-side interconnect access, and accommodates multiple signal paths. By making this single structure multi-functional, the design increases integration capability without proportionally increasing overall device complexity, as the same structural element fulfills several roles simultaneously.
Data Source
AI summary
A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.