Vertical Channel Transistor Bit Line Contact With Plasma-Doped Bottom Region
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving high-concentration doping of the bottom region of semiconductor pillars, particularly for ohmic contact with bit lines, which results in high contact resistance.
Innovation Solution
The process involves forming a semiconductor device with vertical channel transistors, where the semiconductor pillar includes a channel region and two side regions. The second region is doped with a high plasma dopant concentration, and the bit line is in contact with this region, achieving a doping concentration of at least 1e14 atoms/square centimeter at the contact surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping processes are used for the bottom region of semiconductor pillars, then the manufacturing process is simple, but the doping concentration is insufficient and contact resistance is high
Solution Approach 1:
The patent applies local quality by performing plasma doping selectively on the bottom region of the semiconductor pillar. The process targets specific areas (bottom region adjacent to bit line contact region) with higher doping concentration (1e14 to 1e16 atoms/cm²) while maintaining lower doping concentration in other regions, thereby achieving low contact resistance at the contact interface without uniformly increasing doping throughout the entire structure
Solution Approach 2:
The patent changes the doping concentration parameter locally in the bottom region to achieve ohmic contact. By increasing the plasma dopant concentration to 1e14 to 1e16 atoms/cm² in the bottom region specifically, the electrical conductivity is enhanced at the critical contact interface between the bit line and semiconductor pillar, resolving the contact resistance issue
2Reliability
If high doping concentration is achieved in the bottom region, then contact resistance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the bit line contact region and defining the bottom region geometry before performing plasma doping. The semiconductor pillar structure is prepared with its bottom region exposed and positioned adjacent to the bit line contact region, allowing subsequent selective plasma doping to be performed efficiently on the pre-positioned target area, thereby simplifying the overall process despite the specialized doping requirement
3Productivity
If conventional annealing diffusion is used for doping, then the process is well-established, but the doping efficiency is low and high concentration is difficult to achieve
Solution Approach 1:
The patent replaces conventional thermal annealing diffusion with plasma doping technology. Instead of relying on slow thermal diffusion processes that require high temperatures and long times to achieve adequate doping concentrations, the invention uses plasma-based doping methods that can directly introduce dopant atoms into the semiconductor lattice, achieving high doping concentrations (1e14 to 1e16 atoms/cm²) in the bottom region with improved efficiency and reduced processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the contact resistance between the bit line and the semiconductor pillar, enabling ohmic contact and improving the efficiency of the doping process by reducing dependence on annealing diffusion.
Implementation Method 1
a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter
Implementation Method 2
performing plasma doping and annealing diffusion on at least the first side wall region exposed after being covered by the first barrier layer to complete ion doping of the second region
Data Source
AI summary
Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter.