Vertical Transistor Body Contact for Back-Biasing
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Solution Overview
Problem
Vertical transistors face challenges in providing multi-threshold voltages (multi-Vt) necessary for different device applications, as high-performance devices require low Vt for high performance and mobile or standby devices need high Vt for low leakage control, which existing technologies struggle to achieve effectively.
Innovation Solution
The implementation of a vertical transistor device structure with a substrate contact that allows for back bias voltage application, enabling Vt adjustment by forming a conductive material body contact extending from the channel to the substrate, which includes a gate stack and epitaxial source/drain regions, allowing for electrostatic control and threshold voltage shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistor structure is used for scaling, then device density is improved, but control over threshold voltage for different applications deteriorates
Solution Approach 1:
The transistor structure is segmented into distinct regions including source, drain, channel, and gate components that can be independently controlled. The gate is divided into multiple segments (first gate, second gate, third gate) that can apply different voltages to different channel regions, enabling independent control of threshold voltage in various device regions while maintaining the vertical structure for high density.
Solution Approach 2:
The patent changes electrical parameters (gate voltages) to control threshold voltage dynamically. By applying different voltages to different gate segments and controlling channel doping parameters, the device can switch between different threshold voltage states (high-Vt and low-Vt) to meet different application requirements while maintaining the compact vertical structure.
2Power
If high-performance device configuration is used, then drive current is improved, but leakage control deteriorates
Solution Approach 1:
The device structure incorporates dynamic control mechanisms where gate voltages can be adjusted in real-time to optimize performance. The multiple gate segments allow dynamic switching between high-drive-current mode (with lower threshold voltage) and low-leakage mode (with higher threshold voltage), enabling the device to adapt its electrical characteristics based on operational requirements.
Solution Approach 2:
Different regions of the channel are given different local properties through selective doping and independent gate control. The first, second, and third gate segments can apply different voltages to different channel regions, creating local variations in threshold voltage that allow high drive current in performance-critical regions while maintaining low leakage in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides flexible Vt control, enhancing drive current for high-performance devices while managing leakage current, thus addressing the need for multi-Vt capabilities in vertical transistors.
Implementation Method 1
forming a conductive material body contact extending from the channel to the substrate, which includes a gate stack and epitaxial source/drain regions, allowing for electrostatic control and threshold voltage shifting
Data Source
AI summary
A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.