Vertical Transistor Buried Bit Line Contact Resistance
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Solution Overview
Problem
The challenge in semiconductor memory devices is the limited capacity of capacitors due to space occupied by signal transmission layers, and the difficulty in forming a vertical transistor's drain region, which affects mass production efficiency and increases body current leakage.
Innovation Solution
A semiconductor memory device with a vertical transistor and a buried bit line is fabricated using a trench formation process, where a polysilicon layer electrically connects the buried bit line with the drain region, eliminating the need for a separate metal silicide layer and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor is formed with a buried bit line to improve data storage capacity, then the storage node space is preserved and integration is improved, but the fabrication process becomes difficult and mass production efficiency decreases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the buried bit line in the trench, creating the active region with impurity zones, and separately forming the gate structure. This segmentation allows each component to be optimized independently while maintaining overall fabrication efficiency.
Solution Approach 2:
The buried bit line is formed in advance within the trench structure before the active region and gate are created. This preliminary action establishes the foundation for the vertical transistor, enabling subsequent steps to proceed more efficiently and maintain mass production capability.
2Ease of manufacture
If a heavily doped conductive layer is used to form the drain region by diffusion, then the drain region can be created, but the size and dopant concentration cannot be appropriately adjusted
Solution Approach 1:
The patent employs ion implantation with precisely controllable parameters (energy, dose, angle) to form the drain region, replacing the diffusion method. This allows independent adjustment of dopant concentration and spatial distribution, achieving both ease of manufacture and manufacturing precision.
Solution Approach 2:
The thermal diffusion process is replaced with ion implantation, which uses mechanical/electrical fields to directly deposit dopants at controlled depths and concentrations. This substitution provides superior control over dopant placement while simplifying the overall process.
3Reliability
If signal transmission layers are formed between the transistor and capacitor, then electrical connection is enabled, but the capacitor capacity is limited due to occupied space
Solution Approach 1:
The patent transitions from a planar arrangement where signal layers occupy horizontal space to a vertical architecture where the bit line is buried in a trench and connections are made through vertical impurity regions. This dimensional change eliminates the space conflict, enabling both reliable electrical connection and maximum capacitor capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data storage capacity while simplifying the fabrication process, reducing contact resistance, and improving mass production efficiency by forming an ohmic contact directly between the polysilicon layer and the drain region.
Implementation Method 1
an ohmic contact is formed between a drain region of a vertical transistor and a buried bit line
Implementation Method 2
a gate dielectric layer 118 and a gate electrode 120 are sequentially formed on the lateral side of the silicon substrate 110, i.e., on the channel region 116
Data Source
AI summary
A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.