Vertical Transistor Buried Junction Hybrid Doping
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in forming a buried junction in vertical transistors, where precise control over the position and diffusion profile of junctions is required to minimize leakage current and short channel effects, while also reducing contact resistance, which is difficult due to geometrical limitations and variations in the vertical structure.
Innovation Solution
A method involving the formation of trench structures in semiconductor substrates to create wall bodies with selective impurity layers, using different diffusivities of impurities like arsenic and phosphorus to form a buried junction with a first impurity layer and a surrounding second impurity layer, ensuring precise diffusion profiles and reduced contact resistance through hybrid doping techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buried junction is formed in a vertical transistor structure, then the transistor integration density is improved, but the manufacturing precision deteriorates due to difficulty in controlling junction position and diffusion profile
Solution Approach 1:
The patent divides the impurity diffusion process into multiple stages by forming multiple impurity layers with different diffusivities. The first impurity layer (higher diffusivity) and second impurity layer (lower diffusivity) are formed separately and then diffused in sequence, allowing independent control of each layer's diffusion depth and concentration profile. This segmentation enables precise control of the buried junction characteristics while maintaining high integration density.
Solution Approach 2:
The patent applies different impurity concentrations and diffusivities at different locations within the wall body. The first impurity layer is formed with higher concentration and diffusivity near the surface, while the second impurity layer is formed with lower concentration and diffusivity deeper in the structure. This local differentiation allows optimization of both surface contact properties and deep junction formation, resolving the precision control issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise control of junction formation, reducing contact resistance and threshold voltage variations, enabling the integration of more transistors in a limited area while maintaining stable transistor operation by optimizing the diffusion profile and concentration of impurities.
Implementation Method 1
A first impurity layer in the second wall body and a second impurity layer surrounding the first impurity layer are formed by diffusing impurities having different diffusivities in to the portion of the first side surface exposed by the opening
Data Source
AI summary
A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.