Vertical Transistor Capacitor Memory Cell for Long Data Retention
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing area occupation, power consumption, and data retention time, with volatile memories requiring frequent refresh and high power consumption, and non-volatile memories needing high voltage for writing and erasing, which leads to inefficiencies and degradation over time.
Innovation Solution
A semiconductor device comprising a first transistor, a second transistor, and a capacitor, where data is written by accumulating electric charge in the capacitor through the second transistor and held by turning off the second transistor, with the second transistor and capacitor overlapping the first transistor, allowing for low-power operation and reduced area usage, utilizing a wide band gap oxide semiconductor for the second transistor to minimize off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a volatile memory device (DRAM) is used, then the area is small and power consumption is relatively low, but the data retention period is extremely short and frequent refresh operation is required
Solution Approach 1:
The patent combines the structure of volatile memory (small area) with the function of non-volatile memory (long data retention) by using a capacitor that can hold charge for extended periods. The memory element includes a transistor and a capacitor where the capacitor's dielectric layer is formed using an insulating film that maintains charge without requiring frequent refresh operations, thus merging the area efficiency of DRAM with the data retention of non-volatile memory.
Solution Approach 2:
The patent changes the physical parameters of the capacitor's dielectric material by using an insulating film with specific properties (such as high-k materials or specially engineered oxide films) that increase the charge retention capability. This parameter change in the dielectric layer allows the capacitor to maintain voltage and charge for longer periods, extending the data retention period while keeping the memory cell area small.
2Duration of action of stationary object
If a non-volatile memory device (flash memory) is used, then the data retention period is semi-permanent, but large power is consumed due to high voltage requirements for writing and erasing data
Solution Approach 1:
The patent extracts the high voltage requirement from the memory operation by eliminating the need for voltage injection into a floating gate. Instead, data is stored by charging a capacitor through a transistor using standard voltage levels. This removes the harmful high voltage step that causes power consumption and insulating film degradation, while maintaining non-volatile data retention through the charged capacitor state.
Solution Approach 2:
The patent replaces the durable but power-intensive floating gate structure with a simpler capacitor that can be charged and discharged using low voltage. The capacitor serves as a temporary charge storage element that doesn't require high voltage for operation, effectively using a simpler, lower-cost structure to achieve the same data retention function without the power consumption penalty of flash memory.
3Duration of action of stationary object
If flash memory is used for writing and erasing data, then data can be stored semi-permanently, but degradation of the insulating film proceeds in accordance with the number of writing cycles
Solution Approach 1:
The patent converts the harmful effect of high voltage tunneling current that degrades insulating films into a beneficial low-voltage charging process. By storing data in a capacitor rather than injecting charge into a floating gate, the system eliminates the high electric field stress that causes insulating film degradation. The same insulating film that would normally degrade under high voltage tunneling now serves as a stable dielectric for charge storage without degradation.
4Speed
If an SRAM is used, then high speed operation is achieved, but the area is large because one memory element includes at least six transistors
Solution Approach 1:
The patent extracts unnecessary components from the traditional SRAM six-transistor structure by removing redundant transistors and simplifying the circuit topology. The memory element uses a single transistor connected to a capacitor, eliminating the need for multiple access transistors and cross-coupled inverters. This extraction of essential components maintains the core function of fast read/write operations while dramatically reducing the transistor count and overall cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a semiconductor device with reduced area, low power consumption, and extended data retention even after power is stopped, achieving high integration and efficient data storage with reduced manufacturing complexity and cost.
Implementation Method 1
a transistor formed using an oxide semiconductor with a wide band gap has significantly high off-state resistance
Data Source
AI summary
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.