Vertical Transistor Rectangular Channel Bar Current Density
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Solution Overview
Problem
Nanowire transistor devices face challenges in carrying sufficient current due to their small size, necessitating multiple parallel nanowires, which limits their efficiency as transistor devices.
Innovation Solution
The use of vertical transistor devices with rectangular-shaped channel bars extending between a source and drain region, allowing for improved performance and cell area density by increasing the effective width of the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If nanowire transistor devices use small diameter nanowires (ten nanometers or less) to reduce device size, then device size is reduced, but current carrying capability deteriorates
Solution Approach 1:
The patent divides the channel region into multiple parallel nanowires (first nanowire, second nanowire, third nanowire, fourth nanowire) instead of using a single nanowire. This segmentation allows the device to maintain small individual nanowire dimensions for miniaturization while achieving sufficient total current carrying capability through the parallel arrangement of multiple nanowires between source and drain regions.
Solution Approach 2:
The patent transitions from a single-dimensional nanowire structure to a multi-dimensional arrangement by positioning multiple nanowires in parallel between source and drain regions. This dimensional expansion in the vertical channel direction enables the device to overcome the current carrying limitation of individual thin nanowires while preserving the size benefits of nanoscale channels.
2Reliability
If multiple parallel nanowires are used to increase current carrying capability, then current carrying capability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple nanowires into a unified channel structure that is collectively controlled by gate structures. The first and second gate structures control the first and second nanowires, while the third and fourth gate structures control the third and fourth nanowires, creating an integrated multi-nanowire transistor device that functions as a single coherent device rather than separate components.
3Productivity
If traditional silicon planar FETs are replaced with nanowire transistors to continue Moore's law, then scaling capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The channel region is segmented into multiple discrete nanowires with controlled diameters (first, second, third, and fourth nanowires), allowing precise control over channel dimensions. This segmentation enables continued scaling according to Moore's law while managing manufacturing precision through standardized nanowire formation processes.
Data Source
AI summary
In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.