Vertical Access Transistor Structure With Gate-All-Around Channel Control
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Solution Overview
Problem
Conventional planar thin film transistors face challenges due to material limitations and process control issues in patterning small dimensions, leading to insufficient source/drain-to-gate overlap, which adversely impacts device performance.
Innovation Solution
The development of vertical field effect transistors with a self-aligned cylindrical vertical channel that surrounds a stack of a bottom electrode, dielectric pillar, and top electrode, featuring a gate electrode in a gate-all-around configuration to enhance channel control and increase channel width per device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar thin film transistors are used, then fabrication can be performed at low temperatures, but source/drain-to-gate overlap is insufficient leading to poor device performance
Solution Approach 1:
The patent transitions from a conventional planar two-dimensional channel configuration to a vertical three-dimensional channel structure. The vertical channel extends through multiple layers including the gate electrode, enabling gate-all-around control and sufficient source/drain-to-gate overlap while maintaining compatibility with low-temperature fabrication processes for BEOL integration.
Solution Approach 2:
The gate electrode is positioned within the vertical channel structure, with the channel surrounding the gate in a nested configuration. This gate-all-around arrangement provides comprehensive electrostatic control of the channel while maintaining a compact structure suitable for backend-of-line integration.
2Productivity
If planar transistor structures are used, then processing is simpler, but channel width per device area is limited
Solution Approach 1:
By transitioning to a vertical channel architecture, the patent increases the effective channel width per unit device area. The vertical channel allows the channel to extend in the vertical dimension while maintaining a compact lateral footprint, thereby increasing the channel width-to-area ratio and improving current drive capability.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by implementing a vertical channel orientation with gate-all-around configuration. This structural parameter change enables superior electrostatic control and increased channel width per device area compared to conventional planar structures.
3Productivity
If conventional channel designs are used, then manufacturing is easier, but on-current per device area is insufficient
Solution Approach 1:
The vertical channel configuration increases the effective channel width per device area, directly enhancing on-current capability. The three-dimensional structure allows more channel material to be packed into a given device footprint, improving current drive without proportionally increasing the lateral device area.
Solution Approach 2:
The gate-all-around nested structure provides comprehensive control of the vertical channel, enabling superior electrostatics and threshold voltage control. This configuration ensures efficient carrier modulation and high on-current while maintaining manufacturability through standard deposition and etching processes.
Data Source
AI summary
A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.