Vertical Transistor Channel for High Resolution Display Panels
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Solution Overview
Problem
To achieve high resolution in display devices, existing transistor designs face challenges in minimizing the plane size of transistors while maintaining effective operation, particularly in forming non-overlapping source and drain electrodes and optimizing the channel region orientation.
Innovation Solution
A transistor display panel design featuring a semiconductor layer positioned between overlapping gate and data lines, with a gate electrode surrounding the semiconductor layer, and insulating layers to connect electrodes, allowing for a channel region perpendicular to the substrate surface, thereby minimizing transistor size and enhancing resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the transistor plane size is reduced to achieve high resolution, then the resolution is improved, but the difficulty of forming non-overlapping source and drain electrodes increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical structure where the channel extends in the vertical dimension rather than horizontally. This dimensional change allows the source and drain electrodes to be formed without overlapping while maintaining a compact footprint, thereby achieving high resolution without increasing fabrication complexity
Solution Approach 2:
Instead of forming source and drain electrodes side-by-side in the plane, the patent inverts the approach by stacking them vertically with the channel region extending between them in the vertical direction. This inversion resolves the overlapping issue while maintaining electrical functionality
2Ease of manufacture
If the channel region is formed parallel to the substrate surface, then the manufacturing process is simpler, but the transistor plane size increases
Solution Approach 1:
The patent changes the channel region orientation from parallel to the substrate surface to perpendicular to the substrate surface. This vertical orientation allows the transistor to achieve the necessary channel length in the vertical dimension rather than consuming horizontal space, thereby reducing the transistor plane size while maintaining manufacturability through standard vertical deposition processes
3Device complexity
If the gate line and data line are separated to simplify routing, then the routing complexity is reduced, but the aperture ratio decreases
Solution Approach 1:
The patent merges the gate line and data line routing by allowing them to overlap in the planar view while maintaining electrical isolation through vertical separation. The gate electrode is positioned above the data line in the vertical dimension, enabling both lines to share the same planar space without electrical interference, thereby maximizing the aperture ratio while simplifying routing
Solution Approach 2:
The patent resolves the routing conflict by utilizing the vertical dimension to separate the gate and data lines that overlap in the planar view. This three-dimensional routing approach allows both signal lines to occupy the same footprint without electrical interference, maximizing the display aperture while maintaining routing simplicity
Data Source
AI summary
A transistor display panel includes a substrate, a gate line disposed on the substrate, a data line disposed on the substrate, and a transistor disposed on the substrate. The transistor includes a first electrode, a second electrode overlapping the first electrode, a semiconductor layer disposed between the first electrode and the second electrode, and a gate electrode. The semiconductor layer is disposed in an overlapping region where the gate line and the data line overlap each other.