Vertical Transistor Contact Node Using Metal Silicide
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Solution Overview
Problem
Current vertical transistor structures using silicon as contact nodes exhibit high outward contact resistance, hindering the performance improvement of dynamic random access memory (DRAM).
Innovation Solution
A composite contact node is introduced in the vertical transistor structure, comprising a substrate with a protruding structure, an offset layer, and an interlayer formed through an annealing process, which includes a composite conductive layer of metal silicide, such as tungsten silicide, to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon material is used for the contact node, then the manufacturing process is simple, but the outward contact resistance is high
Solution Approach 1:
The patent applies composite materials by forming a composite contact node consisting of a first contact node layer (silicon) and a second contact node layer (metal silicide such as tungsten silicide or titanium silicide). This composite structure combines the advantages of silicon (good integration with existing processes) and metal silicide (low contact resistance), thereby resolving the contradiction between manufacturing simplicity and contact resistance performance.
Solution Approach 2:
The patent changes the material parameter of the contact node from pure silicon to a composite structure including metal silicide. This parameter change (material composition) fundamentally alters the electrical properties, reducing contact resistance while maintaining compatibility with existing manufacturing processes through sequential deposition and annealing steps.
2Reliability
If a composite contact node with metal silicide is formed, then the contact resistance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the offset layer and conductive layer stack before the final contact node formation. The offset layer is deposited and patterned in advance to define the contact region, and the conductive layer is prepared in the stack structure beforehand. This preliminary preparation simplifies the subsequent annealing process and ensures precise contact node formation, reducing overall process complexity despite the composite structure.
Solution Approach 2:
The offset layer serves as an intermediary between the silicon substrate and the metal silicide contact node. It facilitates the formation process by providing a defined interface for the annealing reaction, controlling the diffusion process, and ensuring proper adhesion and electrical contact. This intermediary layer simplifies the complex interaction between silicon and metal silicide during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The composite contact node achieves stable physical and chemical properties with low contact resistance, enhancing the performance of DRAM by providing an efficient electrical connection between the capacitor and gate structures.
Implementation Method 1
subjecting the stack material layer to an annealing process thereby forming an interlayer comprising a composite conductive layer
Implementation Method 2
the offset layer and the conductive layer react together to form the composite conductive layer
Data Source
AI summary
A vertical transistor structure includes a substrate with a protruding structure, an offset layer covering a top surface of the protruding structure, a conductive layer disposed on the offset layer, and an interlayer disposed between the offset layer and the conductive layer to serve as a contact node.