Vertical Transistor Current Dispersion Layer Design
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Solution Overview
Problem
Existing semiconductor devices with trench gate structures face a trade-off between lowering on-resistance and increasing drain withstand voltage, with current dispersion layers not fully optimizing both characteristics.
Innovation Solution
Incorporating a first conductivity type layer with a higher impurity concentration between the drift and channel layers, where at least one end and the center of this layer overlap with the bottom surface insulating film, to enhance drain withstand voltage while reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current dispersion layer is provided between the drift layer and channel layer to lower on-resistance, then on-resistance is reduced, but drain withstand voltage is not sufficiently improved
Solution Approach 1:
The patent applies local quality by creating a current dispersion layer with non-uniform impurity concentration distribution. The impurity concentration is highest at the center portion overlapping the bottom surface insulating film and decreases toward the upper and lower ends. This localized variation in electrical properties optimizes both current dispersion (lowering on-resistance) and electric field distribution (improving drain withstand voltage) in different regions of the same layer.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration within the current dispersion layer. The center portion has higher impurity concentration than the upper and lower ends, creating a gradient structure. This parameter variation allows the layer to simultaneously achieve low on-resistance through high conductivity at the center and high drain withstand voltage through controlled electric field distribution across the entire layer.
2Reliability
If the current dispersion layer is positioned to overlap with the bottom surface insulating film, then drain withstand voltage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses parameter changes in the impurity concentration profile to achieve both high drain withstand voltage and relaxed positioning requirements. By concentrating high impurity concentration at the center portion that overlaps the bottom surface insulating film while having lower concentration at the ends, the design creates a tolerance buffer. The gradient structure ensures optimal performance even with minor positioning variations, reducing the stringency of manufacturing precision requirements.
Data Source
AI summary
In a vertical transistor, to raise a drain withstand voltage while lowering an on-resistance. A drift layer 120 is formed above a drain layer 110, and has a first conductivity type. A gate insulating film 170 is formed on a side wall of a concave portion 142. A bottom surface insulating film 172 is formed on a bottom surface of the concave portion 142. A gate electrode 180 is buried in the concave portion 142. A source layer 150 is formed in a channel layer 140. A first conductivity type layer 130 is located between the channel layer 140 and the drift layer 120. An impurity concentration of the first conductivity type layer 130 is higher than an impurity concentration of the drift layer 120.