Vertical Access Transistor Structure With Self-Aligned Cylindrical Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional planar thin film transistors face limitations in scaling due to material properties and process control challenges, and vertical devices suffer from insufficient source/drain-to-gate overlap, impacting device performance.
Innovation Solution
The development of a semiconductor structure with vertical field effect transistors featuring a cylindrical semiconducting metal oxide channel and a shared gate electrode, where the source and drain electrodes are vertically spaced by a dielectric pillar, and a self-aligned cylindrical channel surrounds a stack of electrodes, providing enhanced channel control and increased channel width per device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar thin film transistors are used, then fabrication can be performed at low temperatures without damaging previously fabricated devices, but scaling is limited due to material properties and process control challenges
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) transistor architecture by stacking source and drain electrodes vertically with a cylindrical channel between them. This dimensional change enables continued scaling of device density without proportionally reducing lateral dimensions, thereby overcoming the scaling limitations of planar TFTs while maintaining compatibility with low-temperature fabrication processes.
2Productivity
If vertical transistor devices are used, then device density is increased, but source/drain-to-gate overlap is insufficient impacting device performance
Solution Approach 1:
The patent implements a nested structure where the cylindrical semiconducting channel is positioned between vertically stacked source and drain electrodes, and the gate electrode completely surrounds the channel in a wrap-around configuration. This nested arrangement maximizes the overlap between source/drain regions and the gate electric field, ensuring strong electrostatic control and high device performance while achieving high vertical integration density.
3Area of moving object
If vertical devices with stacked electrodes are used, then channel width per device area is increased, but channel misalignment issues occur
Solution Approach 1:
The patent forms the cylindrical semiconducting channel material between the source and drain electrodes first, before depositing the gate electrode material. This preliminary formation of the channel structure serves as a template that guides subsequent gate deposition, ensuring automatic self-alignment and eliminating misalignment issues between the channel and gate while maximizing the effective channel width within the available vertical space.
Data Source
AI summary
A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.