Vertical Transistor Gate Self-Alignment via Differential Oxidation
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Solution Overview
Problem
The miniaturization of field-effect transistors in integrated circuits faces challenges with increased static and dynamic power consumption, particularly in achieving high on-state currents and effective electrostatic control, especially for gate-all-around nanowire transistors with short gate lengths, and the industrialization of vertical-channel transistors is hindered by structural differences and manufacturing variability.
Innovation Solution
A process for fabricating vertical-channel transistors involves growing thermal oxides laterally with different growth rates for self-alignment of the gate, using epitaxial growth for semiconductor layers, and employing dielectric layers for spacer formation and gate insulation, allowing for longer gate lengths while maintaining planar integration density, and enabling vertical self-alignment of the gate with respect to the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around nanowire transistors are used to improve electrostatic control, then electrostatic control is improved, but gate length becomes very small making fabrication difficult and limiting on-state current
Solution Approach 1:
The patent transitions from planar transistors to vertical-channel transistors, changing the channel orientation from horizontal to vertical. This dimensional change allows the gate to wrap around the channel in three dimensions (gate-all-around configuration), providing superior electrostatic control while maintaining manufacturable gate lengths through the vertical stacking architecture
2Length of moving object
If vertical-channel nanolayer transistor structures are used to allow longer gate lengths, then gate length is increased, but structural differences create manufacturing variability and alignment difficulties
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial oxide layers and spacer structures before final gate formation. These preliminary structures serve as self-aligned masks and guides that automatically define the gate position and dimensions, eliminating the need for separate alignment steps and reducing manufacturing variability
Solution Approach 2:
The patent employs self-aligned fabrication processes where previously formed structures automatically define the positions of subsequent structures. The sacrificial oxides and spacers serve themselves as alignment references, eliminating the need for external alignment systems and reducing manufacturing complexity
3Ease of manufacture
If conventional deposition and etching processes are used for vertical transistor fabrication, then layer formation is achieved, but gate vertical alignment with channel becomes difficult to ensure
Solution Approach 1:
The patent introduces sacrificial oxide layers as intermediary structures that temporarily exist during fabrication to define the gate position. These intermediary layers are formed through thermal oxidation and serve as self-aligned masks during etching, ensuring precise gate alignment without requiring complex alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrostatic control and increases on-state current while simplifying the manufacturing process by leveraging differential thermal oxidation rates and dielectric growth rates to achieve precise alignment and geometry in vertical transistors, facilitating their industrialization.
Implementation Method 1
growing thermal oxides laterally with different growth rates for self-alignment of the gate
Implementation Method 2
using epitaxial growth for semiconductor layers
Data Source
AI summary
The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.