Vertical Transistor Structure for Short-Channel Display Backplanes
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturizing transistors while maintaining favorable electrical characteristics and achieving high resolution in display devices, particularly for applications like virtual and augmented reality, where transistors with short channel lengths and reduced wiring resistance are required.
Innovation Solution
A semiconductor device comprising a pair of transistors connected in series, with a shared gate electrode and conductive layers, and an insulating layer acting as a spacer, allowing for precise adjustment of channel length and reducing asymmetry in electrical characteristics, enabling miniaturization and high-resolution displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor channel length is shortened to enable miniaturization, then transistor area is reduced, but electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar channel configuration to vertical channel configuration, where the channel extends in the vertical dimension rather than horizontally. This allows the channel length to be decoupled from the transistor footprint area, enabling miniaturization while maintaining adequate channel length for electrical performance
Solution Approach 2:
The semiconductor layer is positioned within a cavity formed in the insulating layer, creating a nested structure where the channel-forming semiconductor layer is contained within the insulating layer's cavity. This nesting enables precise control of channel dimensions and geometry
2Manufacturing precision
If transistor channel length is shortened to increase pixel density, then resolution is improved, but wiring resistance increases
Solution Approach 1:
By forming vertical channels, the patent reduces the horizontal footprint of each transistor, allowing higher pixel density without proportionally increasing wiring resistance, as the vertical current path is more efficient
3Ease of manufacture
If conventional transistor structures are used for miniaturization, then manufacturing is simpler, but asymmetry in electrical characteristics increases
Solution Approach 1:
The patent intentionally creates an asymmetric structure by forming a cavity in the insulating layer and positioning the semiconductor layer within it, with the gate electrode covering the cavity opening. This controlled asymmetry in the vertical direction enables symmetric electrical characteristics by ensuring uniform gate control over the channel
Solution Approach 2:
The insulating layer is selectively removed to form a cavity only in the region where the semiconductor layer will be positioned, creating localized structural differences that enable precise control of channel formation and electrical characteristics
Data Source
AI summary
A semiconductor device including a first transistor, a second transistor, and an insulating layer is provided. The first transistor includes a first semiconductor layer and a first conductive layer. The second transistor includes a second semiconductor layer and a second conductive layer. The insulating layer includes a first side surface over the first conductive layer and a second side surface over the second conductive layer. A gate insulating layer includes a portion facing the first side surface with the first semiconductor layer therebetween and a portion facing the second side surface with the second semiconductor layer therebetween. A gate electrode includes a portion facing the first side surface with the gate insulating layer and the first semiconductor layer therebetween and a portion facing the second side surface with the gate insulating layer and the second semiconductor layer therebetween. The first semiconductor layer is electrically connected to the second semiconductor layer.