Vertical Transistor Display Substrate Reducing Dielectric Thickness
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Solution Overview
Problem
In display technology, silicon-based and oxide semiconductor-based transistors on the same substrate face issues with thick interlayer dielectric layers in oxide semiconductor-based transistors, leading to potential cracking, reduced insulation performance, and decreased reliability due to poor leakage and breakdown.
Innovation Solution
A display substrate design incorporating both horizontal and vertical thin film transistors, where the oxide semiconductor-based transistor eliminates the need for a thick interlayer dielectric layer, with silicon-based and oxide semiconductor-based active layers, and electrodes formed in the same layers to reduce substrate thickness and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick interlayer dielectric layer is used in oxide semiconductor-based transistors, then insulation performance is improved, but cracks are likely to occur reducing reliability
Solution Approach 1:
The patent transitions from a conventional planar transistor structure to a vertical channel structure. The oxide semiconductor layer is formed to extend vertically along the gate electrode, creating a vertical channel that allows current flow in the vertical direction rather than horizontal. This dimensional change enables the transistor to achieve adequate insulation with a thinner interlayer dielectric layer, eliminating the cracking issue associated with thick dielectric layers while maintaining reliability.
Solution Approach 2:
The patent changes the channel length parameter by forming a vertical channel structure. The channel length is defined by the vertical extent of the oxide semiconductor layer along the gate electrode rather than a horizontal distance. This parameter change allows the transistor to achieve proper electrical characteristics with reduced dielectric thickness, preventing cracks while maintaining insulation performance.
2Adaptability or versatility
If both silicon-based and oxide semiconductor-based transistors are manufactured on the same substrate, then device integration is improved, but manufacturing complexity increases due to different transistor structures
Solution Approach 1:
The patent employs a unified bottom-gate transistor structure for both silicon-based and oxide semiconductor-based transistors. The gate electrode, interlayer dielectric layer, and contact structure are formed using the same processes for both transistor types. The only differentiation is the active layer material (silicon or oxide semiconductor), allowing both transistor types to be manufactured on the same substrate with a single set of fabrication processes, thereby reducing manufacturing complexity while maintaining high device integration.
3Ease of manufacture
If lateral transistors are used, then manufacturing process is simplified, but driving capability and stability are limited
Solution Approach 1:
The patent adopts a vertical channel structure where the current flows vertically along the gate electrode rather than horizontally. The source and drain electrodes are positioned at the top and bottom of the vertical channel, respectively. This vertical configuration provides superior electric field control and channel modulation, significantly improving driving capability and stability compared to lateral transistors, while the bottom-gate structure keeps the manufacturing process relatively simple.
Data Source
AI summary
The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. In the display substrate of the present disclosure, a first transistor comprises a first gate electrode, a first electrode, a second electrode, and a first active layer; and a second transistor comprises a second gate electrode, a third electrode, a fourth electrode, and a second active layers, wherein the first active layer comprises a silicon material, the second active layer comprises an oxide semiconductor material, and wherein the third electrode and the first gate electrode are disposed in the same layer, and the fourth electrode and the first electrode, the second electrodes are disposed in the same layer.