Vertical Transistor Extended Drain Region Breakdown Voltage
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Solution Overview
Problem
Conventional transistor devices with extended drain regions face challenges in achieving high breakdown voltage while maintaining a compact device size and scalability, particularly in vertical configurations.
Innovation Solution
The transistor device features a vertical channel region with a horizontally oriented extended drain region, allowing for adjustable breakdown voltage by varying the length of the extended drain region, and incorporates a conductive sidewall spacer structure as a control terminal and a field plate, formed without the need for a photolithographic mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical transistor configuration is used to reduce area occupancy, then device compactness is improved, but achieving high breakdown voltage becomes more difficult
Solution Approach 1:
The patent transitions from a conventional planar extended drain region to a vertical configuration where the extended drain region extends downward from the drain region through the substrate. This dimensional change allows the breakdown voltage to be determined by the vertical depth of the extended drain region rather than horizontal length, enabling high breakdown voltage in a compact footprint.
2Reliability
If the extended drain region length is increased to achieve higher breakdown voltage, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The extended drain region is configured to extend vertically downward from the drain region through the substrate rather than horizontally. This allows the breakdown voltage to be controlled by the vertical depth of the extended drain region, decoupling the breakdown voltage requirement from horizontal area occupation.
3Manufacturing precision
If conventional photolithographic masking is used to form the gate structure, then manufacturing precision is maintained, but device complexity and process steps increase
Solution Approach 1:
The gate structure is formed using the drain region and extended drain region themselves as self-aligned masks during ion implantation. The gate dielectric layer is deposited and then the gate region is formed by ion implantation through the drain region and extended drain region, eliminating the need for separate photolithographic masking steps and reducing process complexity while maintaining precision.
Data Source
AI summary
A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.