Vertical Transistor DRAM with Asymmetric Drain Source Depths
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Solution Overview
Problem
Conventional DRAMs face challenges in reducing leakage current and increasing efficiency due to the limitations of horizontal transistor designs, particularly in vertical trench capacitor structures where the gate channel length affects transistor performance.
Innovation Solution
A dynamic random access memory (DRAM) design featuring vertical transistors with a deeper drain and shallower source, where the depths are controlled through different ion implantation energies and doses, allowing for a longer channel length and reduced leakage current, while simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate channel length is shortened to improve transistor efficiency, then the leakage current increases significantly
Solution Approach 1:
The patent transitions from a conventional horizontal gate channel configuration to a vertical gate channel configuration. By changing the spatial orientation from horizontal to vertical dimension, the design achieves shorter horizontal footprint while maintaining adequate vertical channel length to control leakage current. The vertical transistor structure with deep trench capacitor allows the channel to extend vertically through multiple depth levels, effectively separating the horizontal area constraint from the vertical channel length requirement.
Solution Approach 2:
The patent inverts the traditional transistor architecture by placing the gate vertically rather than horizontally. Instead of extending the channel horizontally across the substrate surface, the channel is formed vertically through the substrate depth. This inversion allows the channel length to be determined by vertical etching depth rather than horizontal lithography dimensions, enabling better leakage control while maintaining compact horizontal footprint.
2Area of stationary object
If vertical transistors are used to decrease horizontal area and increase integration, then the fabrication complexity increases due to deep trench requirements
Solution Approach 1:
The patent merges the formation of the deep trench for the vertical transistor channel with the deep trench for the capacitor structure. By combining these two deep trench requirements into a single fabrication sequence, the patent reduces the number of separate etching and filling operations needed. The shared trench structure serves dual purposes: housing the vertical transistor channel and containing the trench capacitor, thereby simplifying the overall fabrication process while maintaining the vertical transistor architecture.
3Ease of manufacture
If the drain and source are at the same depth to simplify fabrication, then the channel length is reduced and leakage current increases
Solution Approach 1:
The patent applies different local qualities to the drain and source regions by positioning them at different vertical depths within the trench structure. The drain is located at a greater depth than the source, creating a depth gradient that extends the effective channel length vertically. This local differentiation in depth positioning allows the channel to traverse a longer vertical distance, improving leakage control, while the overall structure remains compatible with standard deep trench fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decreases leakage current and enhances transistor efficiency, leading to improved performance and easier control over transistor depths, thereby increasing the effectiveness of the DRAM.
Implementation Method 1
the present invention need only control different energies of the ion implantation processes or an ion dose
Data Source
AI summary
A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.