Vertical Transistor Epitaxial Diffusion Layer Alignment
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Solution Overview
Problem
In vertical transistors, the reduced size of the chip leads to misalignment issues between the upper diffusion layer and the contact pad, causing short circuits and increased interfacial resistance due to the smaller contact area, which is incompatible with performance requirements.
Innovation Solution
The upper diffusion layer is enlarged in the substrate plane direction through selective epitaxial growth, forming a second portion that extends onto an interlayer insulating film, increasing the contact margin and preventing short circuits with the gate electrode without the need for a separate contact pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the chip size is reduced to improve integration density, then the area of upper diffusion layer decreases, but the contact alignment precision deteriorates causing misalignment between contact and upper diffusion layer
Solution Approach 1:
The upper diffusion layer is extended in the vertical direction (substrate normal direction) to form a protruding structure that reaches up to the lower surface of the gate electrode. This vertical extension compensates for the reduced horizontal area, providing a larger contact target area in the vertical dimension while maintaining small chip footprint.
Solution Approach 2:
The upper diffusion layer is formed to protrude upward in advance before contact formation. This preliminary extension ensures that even with alignment variations, the contact will definitely make good contact with the upper diffusion layer, eliminating the need for separate contact pads and improving alignment margin.
2Area of moving object
If the upper diffusion layer area is reduced to minimize chip size, then the contact area between upper diffusion layer and contact pad decreases, but the interfacial resistance increases
Solution Approach 1:
The upper diffusion layer is extended vertically to form a protruding structure that reaches up to the lower surface of the gate electrode. This vertical extension increases the contact area in the vertical dimension, compensating for the reduced horizontal area, thereby maintaining low interfacial resistance while minimizing chip size.
Solution Approach 2:
The upper diffusion layer itself serves dual functions: as the active transistor region and as an extended contact target. By extending the upper diffusion layer vertically, the structure provides its own contact pad function, eliminating the need for separate contact pads and ensuring sufficient contact area without additional structures.
3Manufacturing precision
If a separate contact pad is formed to improve contact alignment, then the contact alignment margin increases, but the device complexity increases due to additional structures
Solution Approach 1:
The upper diffusion layer and contact target are merged into a single structure. The upper diffusion layer is extended vertically to simultaneously serve as the transistor active region and the contact target, eliminating the need for separate contact pads and reducing structural complexity while improving alignment margin.
Solution Approach 2:
The upper diffusion layer performs multiple functions: it serves as the drain region of the transistor, provides the active semiconductor region for current flow, and simultaneously acts as the contact target for electrical connection. This multi-functionality eliminates the need for separate contact pad structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances contact alignment and reduces interfacial resistance, ensuring reliable operation of vertical transistors by maintaining performance while minimizing chip size, thereby addressing the misalignment and resistance issues.
Implementation Method 1
the upper diffusion layer is formed by selective epitaxial growth
Data Source
AI summary
The present invention provides a semiconductor device having a plurality of vertical transistors, which includes, on a substrate, a semiconductor pillar 5; gate electrode 11 provided on the side of the pillar via gate insulating film 10; first diffusion layer 9 connected to the bottom of the pillar; and second diffusion layer 16 connected to the top of the pillar, second diffusion layer 16 includes first portion 14 formed within the area over the pillar, and second portion 15 which is an epitaxial growth layer, formed on the first portion and contacting with insulating film 17 which is provided between adjacent vertical transistors.